bba6f6fc68
So I think the right solution is to simply make pci_enable_device just flip enable bits and move the rest of the work someplace else. However a thorough cleanup is a little extreme for this point in the release cycle, so I think a quick hack that makes the code not stomp the irq when msi irq's are enabled should be the first fix. Then we can later make the code not change the irqs at all. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
132 lines
2.9 KiB
C
132 lines
2.9 KiB
C
#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/arch/hwregs/intr_vect.h>
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void __devinit pcibios_fixup_bus(struct pci_bus *b)
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{
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}
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char * __devinit pcibios_setup(char *str)
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{
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return NULL;
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}
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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unsigned long prot;
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/* Leave vm_pgoff as-is, the PCI space address is the physical
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* address on this platform.
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*/
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prot = pgprot_val(vma->vm_page_prot);
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vma->vm_page_prot = __pgprot(prot);
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/* Write-combine setting is ignored, it is changed via the mtrr
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* interfaces on this platform.
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*/
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if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot))
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return -EAGAIN;
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return 0;
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}
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void
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pcibios_align_resource(void *data, struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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if (res->flags & IORESOURCE_IO) {
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resource_size_t start = res->start;
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if (start & 0x300) {
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start = (start + 0x3ff) & ~0x3ff;
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res->start = start;
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}
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}
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}
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int pcibios_enable_resources(struct pci_dev *dev, int mask)
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{
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u16 cmd, old_cmd;
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int idx;
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struct resource *r;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for(idx=0; idx<6; idx++) {
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/* Only set up the requested stuff */
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if (!(mask & (1<<idx)))
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continue;
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (dev->resource[PCI_ROM_RESOURCE].start)
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cmd |= PCI_COMMAND_MEMORY;
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if (cmd != old_cmd) {
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printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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return 0;
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}
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int pcibios_enable_irq(struct pci_dev *dev)
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{
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dev->irq = EXT_INTR_VECT;
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return 0;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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int err;
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if ((err = pcibios_enable_resources(dev, mask)) < 0)
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return err;
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if (!dev->msi_enabled)
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pcibios_enable_irq(dev);
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return 0;
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}
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int pcibios_assign_resources(void)
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{
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struct pci_dev *dev = NULL;
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int idx;
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struct resource *r;
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while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
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int class = dev->class >> 8;
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/* Don't touch classless devices and host bridges */
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if (!class || class == PCI_CLASS_BRIDGE_HOST)
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continue;
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for(idx=0; idx<6; idx++) {
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r = &dev->resource[idx];
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if (!r->start && r->end)
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pci_assign_resource(dev, idx);
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}
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}
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return 0;
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}
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EXPORT_SYMBOL(pcibios_assign_resources);
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