57a2050c40
Should now be understandable why the thing works ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
89 lines
1.6 KiB
C
89 lines
1.6 KiB
C
/*
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* Malta Platform-specific hooks for SMP operation
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*/
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#include <linux/init.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/smtc.h>
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#include <asm/smtc_ipi.h>
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/* VPE/SMP Prototype implements platform interfaces directly */
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/*
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* Cause the specified action to be performed on a targeted "CPU"
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*/
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void core_send_ipi(int cpu, unsigned int action)
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{
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/* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
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smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
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}
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/*
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* Platform "CPU" startup hook
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*/
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void prom_boot_secondary(int cpu, struct task_struct *idle)
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{
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smtc_boot_secondary(cpu, idle);
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}
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/*
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* Post-config but pre-boot cleanup entry point
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*/
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void prom_init_secondary(void)
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{
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void smtc_init_secondary(void);
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int myvpe;
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/* Don't enable Malta I/O interrupts (IP2) for secondary VPEs */
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myvpe = read_c0_tcbind() & TCBIND_CURVPE;
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if (myvpe != 0) {
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/* Ideally, this should be done only once per VPE, but... */
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clear_c0_status(STATUSF_IP2);
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set_c0_status(STATUSF_IP0 | STATUSF_IP1 | STATUSF_IP3
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| STATUSF_IP4 | STATUSF_IP5 | STATUSF_IP6
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| STATUSF_IP7);
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}
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smtc_init_secondary();
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}
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/*
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* Platform SMP pre-initialization
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*
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* As noted above, we can assume a single CPU for now
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* but it may be multithreaded.
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*/
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void plat_smp_setup(void)
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{
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if (read_c0_config3() & (1<<2))
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mipsmt_build_cpu_map(0);
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}
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void __init plat_prepare_cpus(unsigned int max_cpus)
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{
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if (read_c0_config3() & (1<<2))
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mipsmt_prepare_cpus();
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}
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/*
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* SMP initialization finalization entry point
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*/
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void prom_smp_finish(void)
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{
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smtc_smp_finish();
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}
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/*
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* Hook for after all CPUs are online
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*/
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void prom_cpus_done(void)
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{
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}
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