eb7bd9c461
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper sync procedures as laid out in the Blackfin programming manual. So rather than audit/fix every call location, create helper functions that do the right things in order to safely update these MMRs. Then convert all call sites to use these new helper functions. While we're fixing the code, drop the workaround for anomaly 05000125 as that anomaly applies to old versions of silicon that we do not support. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
173 lines
5.7 KiB
C
173 lines
5.7 KiB
C
/*
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* File: include/asm-blackfin/cplb.h
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* Based on: include/asm-blackfin/mach-bf537/bf537.h
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* Author: Robin Getz <rgetz@blackfin.uclinux.org>
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*
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* Created: 2000
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* Description: Common CPLB definitions for CPLB init
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _CPLB_H
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#define _CPLB_H
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#include <mach/anomaly.h>
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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#if ANOMALY_05000158
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#define ANOMALY_05000158_WORKAROUND 0x200
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#else
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#define ANOMALY_05000158_WORKAROUND 0x0
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#endif
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#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#ifdef CONFIG_BFIN_EXTMEM_WRITEBACK
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
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#elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
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#else
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#define SDRAM_DGENERIC (CPLB_COMMON)
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#endif
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#define SDRAM_DNON_CHBL (CPLB_COMMON)
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#define SDRAM_EBIU (CPLB_COMMON)
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
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#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
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#ifdef CONFIG_SMP
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#define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB)
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#define L2_IMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
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#define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON | PAGE_SIZE_1MB)
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#else
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#define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB)
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# if defined(CONFIG_BFIN_L2_ICACHEABLE)
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# define L2_IMEMORY (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
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# else
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# define L2_IMEMORY ( CPLB_USER_RD | CPLB_VALID | PAGE_SIZE_1MB)
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# endif
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# if defined(CONFIG_BFIN_L2_WRITEBACK)
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# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON | PAGE_SIZE_1MB)
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# elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
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# define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON | PAGE_SIZE_1MB)
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# else
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# define L2_DMEMORY (CPLB_COMMON | PAGE_SIZE_1MB)
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# endif
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#endif /* CONFIG_SMP */
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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#define MAX_CPLBS 16
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
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#define CPLB_ENABLE_ICPLBS_P 4
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#define CPLB_ENABLE_DCPLBS_P 5
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#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
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#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
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#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
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#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
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#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
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#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
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#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
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CPLB_ENABLE_ICPLBS | \
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CPLB_ENABLE_DCPLBS
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#define CPLB_RELOADED 0x0000
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#define CPLB_NO_UNLOCKED 0x0001
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#define CPLB_NO_ADDR_MATCH 0x0002
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#define CPLB_PROT_VIOL 0x0003
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#define CPLB_UNKNOWN_ERR 0x0004
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#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
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#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
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#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
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#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
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#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
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#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
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#define FAULT_RW (1 << 16)
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#define FAULT_USERSUPV (1 << 17)
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#define FAULT_CPLBBITS 0x0000ffff
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#ifndef __ASSEMBLY__
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static inline void _disable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) & ~mask;
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/* CSYNC to ensure load store ordering */
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__builtin_bfin_csync();
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bfin_write32(mmr, ctrl);
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__builtin_bfin_ssync();
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}
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static inline void disable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) & ~mask;
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CSYNC();
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bfin_write32(mmr, ctrl);
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SSYNC();
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}
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#define _disable_dcplb() _disable_cplb(DMEM_CONTROL, ENDCPLB)
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#define disable_dcplb() disable_cplb(DMEM_CONTROL, ENDCPLB)
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#define _disable_icplb() _disable_cplb(IMEM_CONTROL, ENICPLB)
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#define disable_icplb() disable_cplb(IMEM_CONTROL, ENICPLB)
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static inline void _enable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) | mask;
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/* CSYNC to ensure load store ordering */
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__builtin_bfin_csync();
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bfin_write32(mmr, ctrl);
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__builtin_bfin_ssync();
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}
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static inline void enable_cplb(u32 mmr, u32 mask)
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{
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u32 ctrl = bfin_read32(mmr) | mask;
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CSYNC();
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bfin_write32(mmr, ctrl);
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SSYNC();
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}
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#define _enable_dcplb() _enable_cplb(DMEM_CONTROL, ENDCPLB)
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#define enable_dcplb() enable_cplb(DMEM_CONTROL, ENDCPLB)
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#define _enable_icplb() _enable_cplb(IMEM_CONTROL, ENICPLB)
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#define enable_icplb() enable_cplb(IMEM_CONTROL, ENICPLB)
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#endif /* __ASSEMBLY__ */
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#endif /* _CPLB_H */
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