125a00d74e
This patch adds pmc nodes to the device tree files so that the boards will able to use standby capability of MPC837x processors. The MPC837x PMC controllers are compatible with MPC8349 ones (i.e. no deep sleep). sleep = <> properties are used to specify SCCR masks as described in "Specifying Device Power Management Information (sleep property)" chapter in Documentation/powerpc/booting-without-of.txt. Since I2C1 and eSDHC controllers share the same clock source, they are now placed under sleep-nexus nodes. A processor is able to wakeup the boards on LAN events (Wake-On-Lan), console events (with no_console_suspend kernel command line), GPIO events and external IRQs (IRQ1 and IRQ2). The processor can also wakeup the boards by the fourth general purpose timer in GTM1 block, but the GTM wakeup support isn't yet implemented (it's tested to work, but it's unclear how can we use the quite short GTM timers, and how do we want to expose the GTM to userspace). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
431 lines
9.6 KiB
Plaintext
431 lines
9.6 KiB
Plaintext
/*
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* MPC8379E RDB Device Tree Source
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*
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* Copyright 2007, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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compatible = "fsl,mpc8379rdb";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8379@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <32768>;
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i-cache-size = <32768>;
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x10000000>; // 256MB at 0
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};
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localbus@e0005000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
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reg = <0xe0005000 0x1000>;
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interrupts = <77 0x8>;
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interrupt-parent = <&ipic>;
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// CS0 and CS1 are swapped when
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// booting from nand, but the
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// addresses are the same.
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ranges = <0x0 0x0 0xfe000000 0x00800000
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0x1 0x0 0xe0600000 0x00008000
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0x2 0x0 0xf0000000 0x00020000
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0x3 0x0 0xfa000000 0x00008000>;
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flash@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x800000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8379-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x8000>;
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u-boot@0 {
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reg = <0x0 0x100000>;
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read-only;
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};
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kernel@100000 {
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reg = <0x100000 0x300000>;
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};
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fs@400000 {
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reg = <0x400000 0x1c00000>;
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};
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};
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};
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immr@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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gpio1: gpio-controller@c00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
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reg = <0xc00 0x100>;
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interrupts = <74 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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gpio2: gpio-controller@d00 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8379-gpio", "fsl,mpc8349-gpio";
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reg = <0xd00 0x100>;
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interrupts = <75 0x8>;
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interrupt-parent = <&ipic>;
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gpio-controller;
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};
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sleep-nexus {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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sleep = <&pmc 0x0c000000>;
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ranges;
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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dtt@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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at24@50 {
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compatible = "at24,24c256";
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reg = <0x50>;
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};
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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mcu_pio: mcu@a {
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#gpio-cells = <2>;
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compatible = "fsl,mc9s08qg8-mpc8379erdb",
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"fsl,mcu-mpc8349emitx";
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reg = <0x0a>;
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gpio-controller;
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};
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};
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sdhci@2e000 {
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compatible = "fsl,mpc8379-esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <42 0x8>;
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interrupt-parent = <&ipic>;
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/* Filled in by U-Boot */
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clock-frequency = <0>;
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};
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <15 0x8>;
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interrupt-parent = <&ipic>;
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dfsrr;
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};
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spi@7000 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <0x7000 0x1000>;
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interrupts = <16 0x8>;
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interrupt-parent = <&ipic>;
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mode = "cpu";
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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cell-index = <3>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&ipic>;
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interrupts = <38 0x8>;
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phy_type = "ulpi";
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sleep = <&pmc 0x00c00000>;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy2: ethernet-phy@2 {
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interrupt-parent = <&ipic>;
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interrupts = <17 0x8>;
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reg = <0x2>;
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device_type = "ethernet-phy";
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-tbi";
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reg = <0x25520 0x20>;
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <32 0x8 33 0x8 34 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = <&ipic>;
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tbi-handle = <&tbi0>;
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phy-handle = <&phy2>;
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sleep = <&pmc 0xc0000000>;
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fsl,magic-packet;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <35 0x8 36 0x8 37 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = <&ipic>;
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fixed-link = <1 1 1000 0 0>;
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tbi-handle = <&tbi1>;
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sleep = <&pmc 0x30000000>;
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fsl,magic-packet;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <10 0x8>;
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interrupt-parent = <&ipic>;
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};
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crypto@30000 {
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compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
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"fsl,sec2.1", "fsl,sec2.0";
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reg = <0x30000 0x10000>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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fsl,num-channels = <4>;
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fsl,channel-fifo-len = <24>;
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fsl,exec-units-mask = <0x9fe>;
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fsl,descriptor-types-mask = <0x3ab0ebf>;
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sleep = <&pmc 0x03000000>;
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};
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sata@18000 {
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compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
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reg = <0x18000 0x1000>;
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interrupts = <44 0x8>;
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interrupt-parent = <&ipic>;
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sleep = <&pmc 0x000000c0>;
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};
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sata@19000 {
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compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
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reg = <0x19000 0x1000>;
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interrupts = <45 0x8>;
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interrupt-parent = <&ipic>;
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sleep = <&pmc 0x00000030>;
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};
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sata@1a000 {
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compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
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reg = <0x1a000 0x1000>;
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interrupts = <46 0x8>;
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interrupt-parent = <&ipic>;
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sleep = <&pmc 0x0000000c>;
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};
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sata@1b000 {
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compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
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reg = <0x1b000 0x1000>;
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interrupts = <47 0x8>;
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interrupt-parent = <&ipic>;
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sleep = <&pmc 0x00000003>;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: interrupt-controller@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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};
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pmc: power@b00 {
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compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 0x8>;
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interrupt-parent = <&ipic>;
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};
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};
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pci0: pci@e0008500 {
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
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/* IDSEL AD14 IRQ6 inta */
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0x7000 0x0 0x0 0x1 &ipic 22 0x8
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/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
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0x7800 0x0 0x0 0x1 &ipic 21 0x8
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0x7800 0x0 0x0 0x2 &ipic 22 0x8
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0x7800 0x0 0x0 0x4 &ipic 23 0x8
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/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
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0xE000 0x0 0x0 0x1 &ipic 23 0x8
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0xE000 0x0 0x0 0x2 &ipic 21 0x8
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0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
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interrupt-parent = <&ipic>;
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interrupts = <66 0x8>;
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bus-range = <0x0 0x0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
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sleep = <&pmc 0x00010000>;
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clock-frequency = <66666666>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100 /* internal registers */
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0xe0008300 0x8>; /* config space access registers */
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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