0403e38277
Some engines optimize operation by reading ahead in the descriptor chain such that descriptor2 may start execution before descriptor1 completes. If descriptor2 depends on the result from descriptor1 then a fence is required (on descriptor2) to disable this optimization. The async_tx api could implicitly identify dependencies via the 'depend_tx' parameter, but that would constrain cases where the dependency chain only specifies a completion order rather than a data dependency. So, provide an ASYNC_TX_FENCE to explicitly identify data dependencies. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
210 lines
6.8 KiB
C
210 lines
6.8 KiB
C
/*
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* Copyright © 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*/
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#ifndef _ASYNC_TX_H_
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#define _ASYNC_TX_H_
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#include <linux/dmaengine.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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/* on architectures without dma-mapping capabilities we need to ensure
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* that the asynchronous path compiles away
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*/
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#ifdef CONFIG_HAS_DMA
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#define __async_inline
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#else
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#define __async_inline __always_inline
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#endif
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/**
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* dma_chan_ref - object used to manage dma channels received from the
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* dmaengine core.
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* @chan - the channel being tracked
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* @node - node for the channel to be placed on async_tx_master_list
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* @rcu - for list_del_rcu
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* @count - number of times this channel is listed in the pool
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* (for channels with multiple capabiities)
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*/
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struct dma_chan_ref {
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struct dma_chan *chan;
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struct list_head node;
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struct rcu_head rcu;
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atomic_t count;
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};
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/**
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* async_tx_flags - modifiers for the async_* calls
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* @ASYNC_TX_XOR_ZERO_DST: this flag must be used for xor operations where the
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* the destination address is not a source. The asynchronous case handles this
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* implicitly, the synchronous case needs to zero the destination block.
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* @ASYNC_TX_XOR_DROP_DST: this flag must be used if the destination address is
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* also one of the source addresses. In the synchronous case the destination
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* address is an implied source, whereas the asynchronous case it must be listed
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* as a source. The destination address must be the first address in the source
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* array.
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* @ASYNC_TX_ACK: immediately ack the descriptor, precludes setting up a
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* dependency chain
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* @ASYNC_TX_FENCE: specify that the next operation in the dependency
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* chain uses this operation's result as an input
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*/
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enum async_tx_flags {
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ASYNC_TX_XOR_ZERO_DST = (1 << 0),
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ASYNC_TX_XOR_DROP_DST = (1 << 1),
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ASYNC_TX_ACK = (1 << 2),
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ASYNC_TX_FENCE = (1 << 3),
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};
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/**
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* struct async_submit_ctl - async_tx submission/completion modifiers
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* @flags: submission modifiers
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* @depend_tx: parent dependency of the current operation being submitted
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* @cb_fn: callback routine to run at operation completion
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* @cb_param: parameter for the callback routine
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* @scribble: caller provided space for dma/page address conversions
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*/
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struct async_submit_ctl {
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enum async_tx_flags flags;
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struct dma_async_tx_descriptor *depend_tx;
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dma_async_tx_callback cb_fn;
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void *cb_param;
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void *scribble;
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};
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#ifdef CONFIG_DMA_ENGINE
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#define async_tx_issue_pending_all dma_issue_pending_all
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/**
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* async_tx_issue_pending - send pending descriptor to the hardware channel
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* @tx: descriptor handle to retrieve hardware context
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*
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* Note: any dependent operations will have already been issued by
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* async_tx_channel_switch, or (in the case of no channel switch) will
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* be already pending on this channel.
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*/
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static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx)
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{
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if (likely(tx)) {
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struct dma_chan *chan = tx->chan;
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struct dma_device *dma = chan->device;
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dma->device_issue_pending(chan);
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}
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}
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#ifdef CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL
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#include <asm/async_tx.h>
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#else
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#define async_tx_find_channel(dep, type, dst, dst_count, src, src_count, len) \
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__async_tx_find_channel(dep, type)
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struct dma_chan *
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__async_tx_find_channel(struct async_submit_ctl *submit,
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enum dma_transaction_type tx_type);
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#endif /* CONFIG_ARCH_HAS_ASYNC_TX_FIND_CHANNEL */
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#else
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static inline void async_tx_issue_pending_all(void)
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{
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do { } while (0);
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}
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static inline void async_tx_issue_pending(struct dma_async_tx_descriptor *tx)
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{
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do { } while (0);
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}
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static inline struct dma_chan *
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async_tx_find_channel(struct async_submit_ctl *submit,
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enum dma_transaction_type tx_type, struct page **dst,
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int dst_count, struct page **src, int src_count,
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size_t len)
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{
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return NULL;
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}
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#endif
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/**
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* async_tx_sync_epilog - actions to take if an operation is run synchronously
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* @cb_fn: function to call when the transaction completes
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* @cb_fn_param: parameter to pass to the callback routine
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*/
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static inline void
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async_tx_sync_epilog(struct async_submit_ctl *submit)
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{
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if (submit->cb_fn)
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submit->cb_fn(submit->cb_param);
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}
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typedef union {
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unsigned long addr;
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struct page *page;
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dma_addr_t dma;
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} addr_conv_t;
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static inline void
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init_async_submit(struct async_submit_ctl *args, enum async_tx_flags flags,
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struct dma_async_tx_descriptor *tx,
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dma_async_tx_callback cb_fn, void *cb_param,
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addr_conv_t *scribble)
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{
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args->flags = flags;
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args->depend_tx = tx;
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args->cb_fn = cb_fn;
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args->cb_param = cb_param;
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args->scribble = scribble;
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}
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void async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
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struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_xor(struct page *dest, struct page **src_list, unsigned int offset,
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int src_cnt, size_t len, struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_xor_val(struct page *dest, struct page **src_list, unsigned int offset,
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int src_cnt, size_t len, enum sum_check_flags *result,
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struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_memcpy(struct page *dest, struct page *src, unsigned int dest_offset,
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unsigned int src_offset, size_t len,
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struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_memset(struct page *dest, int val, unsigned int offset,
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size_t len, struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *async_trigger_callback(struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_gen_syndrome(struct page **blocks, unsigned int offset, int src_cnt,
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size_t len, struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_syndrome_val(struct page **blocks, unsigned int offset, int src_cnt,
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size_t len, enum sum_check_flags *pqres, struct page *spare,
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struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_raid6_2data_recov(int src_num, size_t bytes, int faila, int failb,
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struct page **ptrs, struct async_submit_ctl *submit);
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struct dma_async_tx_descriptor *
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async_raid6_datap_recov(int src_num, size_t bytes, int faila,
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struct page **ptrs, struct async_submit_ctl *submit);
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void async_tx_quiesce(struct dma_async_tx_descriptor **tx);
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#endif /* _ASYNC_TX_H_ */
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