f65e4fa8e0
Now that finally all supported versions of binutils have functioning support for .subsection use .subsection to tweak the branch prediction I did not modify the R10000 errata variants because it seems unclear if this will invalidate the workaround which actually relies on the cheesy prediction of branch likely to cause a misspredict if the sc was successful. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
361 lines
8.7 KiB
C
361 lines
8.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_SYSTEM_H
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#define _ASM_SYSTEM_H
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#include <linux/types.h>
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#include <linux/irqflags.h>
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#include <asm/addrspace.h>
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#include <asm/barrier.h>
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#include <asm/cpu-features.h>
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#include <asm/dsp.h>
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#include <asm/war.h>
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/*
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* switch_to(n) should switch tasks to task nr n, first
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* checking that n isn't the current task, in which case it does nothing.
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*/
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extern asmlinkage void *resume(void *last, void *next, void *next_ti);
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struct task_struct;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/*
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* Handle the scheduler resume end of FPU affinity management. We do this
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* inline to try to keep the overhead down. If we have been forced to run on
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* a "CPU" with an FPU because of a previous high level of FP computation,
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* but did not actually use the FPU during the most recent time-slice (CU1
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* isn't set), we undo the restriction on cpus_allowed.
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*
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* We're not calling set_cpus_allowed() here, because we have no need to
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* force prompt migration - we're already switching the current CPU to a
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* different thread.
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*/
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#define switch_to(prev,next,last) \
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do { \
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if (cpu_has_fpu && \
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(prev->thread.mflags & MF_FPUBOUND) && \
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(!(KSTK_STATUS(prev) & ST0_CU1))) { \
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prev->thread.mflags &= ~MF_FPUBOUND; \
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prev->cpus_allowed = prev->thread.user_cpus_allowed; \
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} \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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next->thread.emulated_fp = 0; \
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(last) = resume(prev, next, next->thread_info); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#else
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#define switch_to(prev,next,last) \
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do { \
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if (cpu_has_dsp) \
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__save_dsp(prev); \
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(last) = resume(prev, next, task_thread_info(next)); \
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if (cpu_has_dsp) \
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__restore_dsp(current); \
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} while(0)
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#endif
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection,
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* it needs a way to flush as much of the CPU's caches as possible.
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*
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* TODO: fill this in!
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*/
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static inline void sched_cacheflush(void)
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{
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}
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static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
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{
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__u32 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %3 # xchg_u32 \n"
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" .set mips0 \n"
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" move %2, %z4 \n"
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" .set mips3 \n"
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" sc %2, %1 \n"
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" beqz %2, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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return retval;
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}
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#ifdef CONFIG_64BIT
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static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
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{
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__u64 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqzl %2, 1b \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long dummy;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %3 # xchg_u64 \n"
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" move %2, %z4 \n"
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" scd %2, %1 \n"
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" beqz %2, 2f \n"
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" .subsection 2 \n"
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"2: b 1b \n"
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" .previous \n"
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" .set mips0 \n"
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: "=&r" (retval), "=m" (*m), "=&r" (dummy)
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: "R" (*m), "Jr" (val)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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*m = val;
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local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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return retval;
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}
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#else
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extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
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#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid xchg(). */
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extern void __xchg_called_with_bad_pointer(void);
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static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
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{
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switch (size) {
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case 4:
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return __xchg_u32(ptr, x);
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case 8:
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return __xchg_u64(ptr, x);
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
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#define tas(ptr) (xchg((ptr),1))
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
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unsigned long new)
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{
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__u32 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqzl $1, 1b \n"
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: ll %0, %2 # __cmpxchg_u32 \n"
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" bne %0, %z3, 2f \n"
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" .set mips0 \n"
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" move $1, %z4 \n"
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" .set mips3 \n"
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" sc $1, %1 \n"
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" beqz $1, 3f \n"
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"2: \n"
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" .subsection 2 \n"
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"3: b 1b \n"
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" .previous \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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return retval;
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}
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#ifdef CONFIG_64BIT
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static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
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unsigned long new)
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{
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__u64 retval;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: lld %0, %2 # __cmpxchg_u64 \n"
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" bne %0, %z3, 2f \n"
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" move $1, %z4 \n"
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" scd $1, %1 \n"
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" beqzl $1, 1b \n"
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"2: \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__(
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" .set push \n"
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" .set noat \n"
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" .set mips3 \n"
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"1: lld %0, %2 # __cmpxchg_u64 \n"
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" bne %0, %z3, 2f \n"
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" move $1, %z4 \n"
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" scd $1, %1 \n"
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" beqz $1, 3f \n"
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"2: \n"
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" .subsection 2 \n"
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"3: b 1b \n"
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" .previous \n"
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" .set pop \n"
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: "=&r" (retval), "=R" (*m)
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: "R" (*m), "Jr" (old), "Jr" (new)
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: "memory");
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} else {
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unsigned long flags;
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local_irq_save(flags);
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retval = *m;
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if (retval == old)
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*m = new;
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local_irq_restore(flags); /* implies memory barrier */
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}
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smp_mb();
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return retval;
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}
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#else
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extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
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volatile int * m, unsigned long old, unsigned long new);
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#define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
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extern void set_handler (unsigned long offset, void *addr, unsigned long len);
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extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
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extern void *set_vi_handler (int n, void *addr);
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extern void *set_except_vector(int n, void *addr);
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extern unsigned long ebase;
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extern void per_cpu_trap_init(void);
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extern int stop_a_enabled;
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/*
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* See include/asm-ia64/system.h; prevents deadlock on SMP
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* systems.
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*/
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define arch_align_stack(x) (x)
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#endif /* _ASM_SYSTEM_H */
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