939b787130
Move the IRQ stub generation to assembly to simplify it and for consistency with 32 bits. Doing it in a C file with asm() statements doesn't help clarity, and it prevents some optimizations. Shrink the IRQ stubs down to just over four bytes per (we fit seven into a 32-byte chunk.) This shrinks the total icache consumption of the IRQ stubs down to an even kilobyte, if all of them are in active use. The downside is that we end up with a double jump, which could have a negative effect on some pipelines. The double jump is always inside the same cacheline on any modern chips. To get the most effect, cache-align the IRQ stubs. This makes the 64-bit code match changes already done to the 32-bit code, and should open up irqinit*.c for unification. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
164 lines
4.2 KiB
C
164 lines
4.2 KiB
C
#include <linux/linkage.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/bitops.h>
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#include <asm/acpi.h>
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#include <asm/atomic.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/hw_irq.h>
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#include <asm/pgtable.h>
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#include <asm/delay.h>
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#include <asm/desc.h>
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#include <asm/apic.h>
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#include <asm/i8259.h>
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/*
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* ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
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* (these are usually mapped to vectors 0x30-0x3f)
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*/
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/*
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* The IO-APIC gives us many more interrupt sources. Most of these
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* are unused but an SMP system is supposed to have enough memory ...
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* sometimes (mostly wrt. hw bugs) we get corrupted vectors all
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* across the spectrum, so we really want to be prepared to get all
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* of these. Plus, more powerful systems might have more than 64
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* IO-APIC registers.
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*
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* (these are usually mapped into the 0x30-0xff vector range)
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*/
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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.handler = no_action,
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.mask = CPU_MASK_NONE,
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.name = "cascade",
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... IRQ0_VECTOR - 1] = -1,
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[IRQ0_VECTOR] = 0,
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[IRQ1_VECTOR] = 1,
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[IRQ2_VECTOR] = 2,
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[IRQ3_VECTOR] = 3,
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[IRQ4_VECTOR] = 4,
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[IRQ5_VECTOR] = 5,
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[IRQ6_VECTOR] = 6,
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[IRQ7_VECTOR] = 7,
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[IRQ8_VECTOR] = 8,
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[IRQ9_VECTOR] = 9,
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[IRQ10_VECTOR] = 10,
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[IRQ11_VECTOR] = 11,
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[IRQ12_VECTOR] = 12,
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[IRQ13_VECTOR] = 13,
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[IRQ14_VECTOR] = 14,
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[IRQ15_VECTOR] = 15,
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[IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
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};
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void __init init_ISA_irqs(void)
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{
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int i;
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init_bsp_APIC();
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init_8259A(0);
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for (i = 0; i < 16; i++) {
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/* first time call this irq_desc */
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struct irq_desc *desc = irq_to_desc(i);
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desc->status = IRQ_DISABLED;
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desc->action = NULL;
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desc->depth = 1;
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/*
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* 16 old-style INTA-cycle interrupts:
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*/
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set_irq_chip_and_handler_name(i, &i8259A_chip,
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handle_level_irq, "XT");
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}
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}
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void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
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static void __init smp_intr_init(void)
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{
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#ifdef CONFIG_SMP
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/*
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* IPI, driven by wakeup.
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*/
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alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
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/* IPIs for invalidation */
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
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alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
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/* IPI for generic function call */
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alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
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/* IPI for generic single function call */
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alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
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call_function_single_interrupt);
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/* Low priority IPI to cleanup after moving an irq */
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set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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#endif
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}
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static void __init apic_intr_init(void)
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{
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smp_intr_init();
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alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
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alloc_intr_gate(THRESHOLD_APIC_VECTOR, threshold_interrupt);
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/* self generated IPI for local APIC timer */
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alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
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/* IPI vectors for APIC spurious and error interrupts */
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alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
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alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
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}
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void __init native_init_IRQ(void)
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{
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int i;
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init_ISA_irqs();
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/*
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* Cover the whole vector space, no vector can escape
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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*/
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for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
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int vector = FIRST_EXTERNAL_VECTOR + i;
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if (vector != IA32_SYSCALL_VECTOR)
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set_intr_gate(vector, interrupt[i]);
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}
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apic_intr_init();
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if (!acpi_ioapic)
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setup_irq(2, &irq2);
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}
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