2f01a1f588
wl12xx is a driver for TI wl1251 802.11 chipset designed for embedded devices, supporting both SDIO and SPI busses. Currently the driver supports only SPI. Adding support 1253 (the 5 GHz version) should be relatively easy. More information here: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=4711&navigationId=12494&templateId=6123 (Collapsed original sequence of pre-merge patches into single commit for initial merge. -- JWL) Signed-off-by: Kalle Valo <kalle.valo@nokia.com> Signed-off-by: Bob Copeland <me@bobcopeland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
123 lines
3.2 KiB
C
123 lines
3.2 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (c) 1998-2007 Texas Instruments Incorporated
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Kalle Valo <kalle.valo@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL12XX_RX_H__
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#define __WL12XX_RX_H__
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#include <linux/bitops.h>
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/*
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* RX PATH
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*
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* The Rx path uses a double buffer and an rx_contro structure, each located
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* at a fixed address in the device memory. The host keeps track of which
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* buffer is available and alternates between them on a per packet basis.
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* The size of each of the two buffers is large enough to hold the longest
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* 802.3 packet.
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* The RX path goes like that:
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* 1) The target generates an interrupt each time a new packet is received.
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* There are 2 RX interrupts, one for each buffer.
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* 2) The host reads the received packet from one of the double buffers.
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* 3) The host triggers a target interrupt.
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* 4) The target prepares the next RX packet.
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*/
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#define WL12XX_RX_MAX_RSSI -30
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#define WL12XX_RX_MIN_RSSI -95
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#define WL12XX_RX_ALIGN_TO 4
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#define WL12XX_RX_ALIGN(len) (((len) + WL12XX_RX_ALIGN_TO - 1) & \
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~(WL12XX_RX_ALIGN_TO - 1))
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#define SHORT_PREAMBLE_BIT BIT(0)
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#define OFDM_RATE_BIT BIT(6)
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#define PBCC_RATE_BIT BIT(7)
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#define PLCP_HEADER_LENGTH 8
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#define RX_DESC_PACKETID_SHIFT 11
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#define RX_MAX_PACKET_ID 3
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#define RX_DESC_VALID_FCS 0x0001
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#define RX_DESC_MATCH_RXADDR1 0x0002
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#define RX_DESC_MCAST 0x0004
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#define RX_DESC_STAINTIM 0x0008
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#define RX_DESC_VIRTUAL_BM 0x0010
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#define RX_DESC_BCAST 0x0020
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#define RX_DESC_MATCH_SSID 0x0040
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#define RX_DESC_MATCH_BSSID 0x0080
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#define RX_DESC_ENCRYPTION_MASK 0x0300
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#define RX_DESC_MEASURMENT 0x0400
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#define RX_DESC_SEQNUM_MASK 0x1800
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#define RX_DESC_MIC_FAIL 0x2000
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#define RX_DESC_DECRYPT_FAIL 0x4000
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struct wl12xx_rx_descriptor {
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u32 timestamp; /* In microseconds */
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u16 length; /* Paylod length, including headers */
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u16 flags;
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/*
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* 0 - 802.11
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* 1 - 802.3
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* 2 - IP
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* 3 - Raw Codec
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*/
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u8 type;
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/*
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* Recevied Rate:
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* 0x0A - 1MBPS
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* 0x14 - 2MBPS
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* 0x37 - 5_5MBPS
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* 0x0B - 6MBPS
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* 0x0F - 9MBPS
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* 0x6E - 11MBPS
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* 0x0A - 12MBPS
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* 0x0E - 18MBPS
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* 0xDC - 22MBPS
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* 0x09 - 24MBPS
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* 0x0D - 36MBPS
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* 0x08 - 48MBPS
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* 0x0C - 54MBPS
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*/
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u8 rate;
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u8 mod_pre; /* Modulation and preamble */
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u8 channel;
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/*
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* 0 - 2.4 Ghz
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* 1 - 5 Ghz
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*/
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u8 band;
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s8 rssi; /* in dB */
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u8 rcpi; /* in dB */
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u8 snr; /* in dB */
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} __attribute__ ((packed));
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void wl12xx_rx(struct wl12xx *wl);
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#endif
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