2f01a1f588
wl12xx is a driver for TI wl1251 802.11 chipset designed for embedded devices, supporting both SDIO and SPI busses. Currently the driver supports only SPI. Adding support 1253 (the 5 GHz version) should be relatively easy. More information here: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?contentId=4711&navigationId=12494&templateId=6123 (Collapsed original sequence of pre-merge patches into single commit for initial merge. -- JWL) Signed-off-by: Kalle Valo <kalle.valo@nokia.com> Signed-off-by: Bob Copeland <me@bobcopeland.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
166 lines
4.0 KiB
C
166 lines
4.0 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Kalle Valo <kalle.valo@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __WL1251_H__
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#define __WL1251_H__
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#include <linux/bitops.h>
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#include "wl12xx.h"
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#include "acx.h"
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#define WL1251_FW_NAME "wl1251-fw.bin"
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#define WL1251_NVS_NAME "wl1251-nvs.bin"
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#define WL1251_POWER_ON_SLEEP 10 /* in miliseconds */
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void wl1251_setup(struct wl12xx *wl);
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struct wl1251_acx_memory {
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__le16 num_stations; /* number of STAs to be supported. */
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u16 reserved_1;
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/*
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* Nmber of memory buffers for the RX mem pool.
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* The actual number may be less if there are
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* not enough blocks left for the minimum num
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* of TX ones.
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*/
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u8 rx_mem_block_num;
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u8 reserved_2;
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u8 num_tx_queues; /* From 1 to 16 */
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u8 host_if_options; /* HOST_IF* */
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u8 tx_min_mem_block_num;
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u8 num_ssid_profiles;
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__le16 debug_buffer_size;
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} __attribute__ ((packed));
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#define ACX_RX_DESC_MIN 1
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#define ACX_RX_DESC_MAX 127
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#define ACX_RX_DESC_DEF 32
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struct wl1251_acx_rx_queue_config {
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u8 num_descs;
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u8 pad;
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u8 type;
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u8 priority;
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__le32 dma_address;
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} __attribute__ ((packed));
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#define ACX_TX_DESC_MIN 1
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#define ACX_TX_DESC_MAX 127
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#define ACX_TX_DESC_DEF 16
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struct wl1251_acx_tx_queue_config {
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u8 num_descs;
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u8 pad[2];
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u8 attributes;
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} __attribute__ ((packed));
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#define MAX_TX_QUEUE_CONFIGS 5
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#define MAX_TX_QUEUES 4
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struct wl1251_acx_config_memory {
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struct acx_header header;
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struct wl1251_acx_memory mem_config;
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struct wl1251_acx_rx_queue_config rx_queue_config;
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struct wl1251_acx_tx_queue_config tx_queue_config[MAX_TX_QUEUE_CONFIGS];
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} __attribute__ ((packed));
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struct wl1251_acx_mem_map {
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struct acx_header header;
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void *code_start;
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void *code_end;
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void *wep_defkey_start;
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void *wep_defkey_end;
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void *sta_table_start;
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void *sta_table_end;
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void *packet_template_start;
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void *packet_template_end;
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void *queue_memory_start;
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void *queue_memory_end;
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void *packet_memory_pool_start;
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void *packet_memory_pool_end;
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void *debug_buffer1_start;
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void *debug_buffer1_end;
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void *debug_buffer2_start;
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void *debug_buffer2_end;
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/* Number of blocks FW allocated for TX packets */
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u32 num_tx_mem_blocks;
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/* Number of blocks FW allocated for RX packets */
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u32 num_rx_mem_blocks;
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} __attribute__ ((packed));
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/*************************************************************************
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Host Interrupt Register (WiLink -> Host)
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**************************************************************************/
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/* RX packet is ready in Xfer buffer #0 */
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#define WL1251_ACX_INTR_RX0_DATA BIT(0)
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/* TX result(s) are in the TX complete buffer */
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#define WL1251_ACX_INTR_TX_RESULT BIT(1)
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/* OBSOLETE */
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#define WL1251_ACX_INTR_TX_XFR BIT(2)
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/* RX packet is ready in Xfer buffer #1 */
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#define WL1251_ACX_INTR_RX1_DATA BIT(3)
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/* Event was entered to Event MBOX #A */
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#define WL1251_ACX_INTR_EVENT_A BIT(4)
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/* Event was entered to Event MBOX #B */
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#define WL1251_ACX_INTR_EVENT_B BIT(5)
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/* OBSOLETE */
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#define WL1251_ACX_INTR_WAKE_ON_HOST BIT(6)
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/* Trace meassge on MBOX #A */
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#define WL1251_ACX_INTR_TRACE_A BIT(7)
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/* Trace meassge on MBOX #B */
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#define WL1251_ACX_INTR_TRACE_B BIT(8)
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/* Command processing completion */
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#define WL1251_ACX_INTR_CMD_COMPLETE BIT(9)
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/* Init sequence is done */
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#define WL1251_ACX_INTR_INIT_COMPLETE BIT(14)
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#define WL1251_ACX_INTR_ALL 0xFFFFFFFF
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#endif
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