94dee171df
> #define hw_interrupt_type irq_chip > typedef struct irq_chip hw_irq_controller; > #define no_irq_type no_irq_chip > typedef struct irq_desc irq_desc_t; Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
135 lines
3.5 KiB
C
135 lines
3.5 KiB
C
/*
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* arch/mips/emma2rh/common/irq_emma2rh.c
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* This file defines the irq handler for EMMA2RH.
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*
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* Copyright (C) NEC Electronics Corporation 2005-2006
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*
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* This file is based on the arch/mips/ddb5xxx/ddb5477/irq_5477.c
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* EMMA2RH defines 64 IRQs.
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*
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* This file exports one function:
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* emma2rh_irq_init(u32 irq_base);
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*/
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#include <linux/interrupt.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <asm/debug.h>
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#include <asm/emma2rh/emma2rh.h>
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/* number of total irqs supported by EMMA2RH */
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#define NUM_EMMA2RH_IRQ 96
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static int emma2rh_irq_base = -1;
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void ll_emma2rh_irq_enable(int);
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void ll_emma2rh_irq_disable(int);
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static void emma2rh_irq_enable(unsigned int irq)
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{
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ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
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}
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static void emma2rh_irq_disable(unsigned int irq)
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{
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ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
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}
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static unsigned int emma2rh_irq_startup(unsigned int irq)
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{
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emma2rh_irq_enable(irq);
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return 0;
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}
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#define emma2rh_irq_shutdown emma2rh_irq_disable
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static void emma2rh_irq_ack(unsigned int irq)
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{
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/* disable interrupt - some handler will re-enable the irq
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* and if the interrupt is leveled, we will have infinite loop
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*/
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ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
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}
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static void emma2rh_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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ll_emma2rh_irq_enable(irq - emma2rh_irq_base);
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}
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struct irq_chip emma2rh_irq_controller = {
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.typename = "emma2rh_irq",
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.startup = emma2rh_irq_startup,
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.shutdown = emma2rh_irq_shutdown,
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.enable = emma2rh_irq_enable,
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.disable = emma2rh_irq_disable,
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.ack = emma2rh_irq_ack,
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.end = emma2rh_irq_end,
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.set_affinity = NULL /* no affinity stuff for UP */
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};
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void emma2rh_irq_init(u32 irq_base)
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{
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u32 i;
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for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].handler = &emma2rh_irq_controller;
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}
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emma2rh_irq_base = irq_base;
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}
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void ll_emma2rh_irq_enable(int emma2rh_irq)
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{
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u32 reg_value;
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u32 reg_bitmask;
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u32 reg_index;
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reg_index = EMMA2RH_BHIF_INT_EN_0
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+ (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
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* (emma2rh_irq / 32);
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reg_value = emma2rh_in32(reg_index);
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reg_bitmask = 0x1 << (emma2rh_irq % 32);
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db_assert((reg_value & reg_bitmask) == 0);
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emma2rh_out32(reg_index, reg_value | reg_bitmask);
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}
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void ll_emma2rh_irq_disable(int emma2rh_irq)
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{
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u32 reg_value;
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u32 reg_bitmask;
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u32 reg_index;
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reg_index = EMMA2RH_BHIF_INT_EN_0
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+ (EMMA2RH_BHIF_INT_EN_1 - EMMA2RH_BHIF_INT_EN_0)
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* (emma2rh_irq / 32);
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reg_value = emma2rh_in32(reg_index);
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reg_bitmask = 0x1 << (emma2rh_irq % 32);
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db_assert((reg_value & reg_bitmask) != 0);
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emma2rh_out32(reg_index, reg_value & ~reg_bitmask);
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}
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