162b96e63e
All the necessary fields for handling an ioat2,3 ring entry can fit into one cacheline. Move ->len prior to ->txd in struct ioat_ring_ent, and move allocation of these entries to a hw-cache-aligned kmem cache to reduce the number of cachelines dirtied for descriptor management. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
/*
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* Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef IOATDMA_V2_H
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#define IOATDMA_V2_H
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#include <linux/dmaengine.h>
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#include "dma.h"
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#include "hw.h"
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extern int ioat_pending_level;
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/*
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* workaround for IOAT ver.3.0 null descriptor issue
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* (channel returns error when size is 0)
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*/
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#define NULL_DESC_BUFFER_SIZE 1
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#define IOAT_MAX_ORDER 16
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#define ioat_get_alloc_order() \
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(min(ioat_ring_alloc_order, IOAT_MAX_ORDER))
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#define ioat_get_max_alloc_order() \
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(min(ioat_ring_max_alloc_order, IOAT_MAX_ORDER))
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/* struct ioat2_dma_chan - ioat v2 / v3 channel attributes
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* @base: common ioat channel parameters
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* @xfercap_log; log2 of channel max transfer length (for fast division)
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* @head: allocated index
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* @issued: hardware notification point
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* @tail: cleanup index
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* @pending: lock free indicator for issued != head
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* @dmacount: identical to 'head' except for occasionally resetting to zero
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* @alloc_order: log2 of the number of allocated descriptors
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* @ring: software ring buffer implementation of hardware ring
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* @ring_lock: protects ring attributes
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*/
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struct ioat2_dma_chan {
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struct ioat_chan_common base;
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size_t xfercap_log;
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u16 head;
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u16 issued;
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u16 tail;
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u16 dmacount;
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u16 alloc_order;
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int pending;
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struct ioat_ring_ent **ring;
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spinlock_t ring_lock;
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};
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static inline struct ioat2_dma_chan *to_ioat2_chan(struct dma_chan *c)
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{
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struct ioat_chan_common *chan = to_chan_common(c);
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return container_of(chan, struct ioat2_dma_chan, base);
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}
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static inline u16 ioat2_ring_mask(struct ioat2_dma_chan *ioat)
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{
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return (1 << ioat->alloc_order) - 1;
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}
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/* count of descriptors in flight with the engine */
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static inline u16 ioat2_ring_active(struct ioat2_dma_chan *ioat)
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{
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return (ioat->head - ioat->tail) & ioat2_ring_mask(ioat);
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}
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/* count of descriptors pending submission to hardware */
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static inline u16 ioat2_ring_pending(struct ioat2_dma_chan *ioat)
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{
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return (ioat->head - ioat->issued) & ioat2_ring_mask(ioat);
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}
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static inline u16 ioat2_ring_space(struct ioat2_dma_chan *ioat)
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{
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u16 num_descs = ioat2_ring_mask(ioat) + 1;
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u16 active = ioat2_ring_active(ioat);
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BUG_ON(active > num_descs);
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return num_descs - active;
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}
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/* assumes caller already checked space */
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static inline u16 ioat2_desc_alloc(struct ioat2_dma_chan *ioat, u16 len)
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{
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ioat->head += len;
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return ioat->head - len;
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}
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static inline u16 ioat2_xferlen_to_descs(struct ioat2_dma_chan *ioat, size_t len)
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{
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u16 num_descs = len >> ioat->xfercap_log;
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num_descs += !!(len & ((1 << ioat->xfercap_log) - 1));
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return num_descs;
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}
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struct ioat_ring_ent {
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struct ioat_dma_descriptor *hw;
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size_t len;
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struct dma_async_tx_descriptor txd;
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#ifdef DEBUG
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int id;
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#endif
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};
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static inline struct ioat_ring_ent *
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ioat2_get_ring_ent(struct ioat2_dma_chan *ioat, u16 idx)
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{
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return ioat->ring[idx & ioat2_ring_mask(ioat)];
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}
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static inline void ioat2_set_chainaddr(struct ioat2_dma_chan *ioat, u64 addr)
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{
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struct ioat_chan_common *chan = &ioat->base;
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writel(addr & 0x00000000FFFFFFFF,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
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writel(addr >> 32,
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chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
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}
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int __devinit ioat2_dma_probe(struct ioatdma_device *dev, int dca);
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int __devinit ioat3_dma_probe(struct ioatdma_device *dev, int dca);
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struct dca_provider * __devinit ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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struct dca_provider * __devinit ioat3_dca_init(struct pci_dev *pdev, void __iomem *iobase);
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extern struct kmem_cache *ioat2_cache;
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#endif /* IOATDMA_V2_H */
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