177dfcd80f
The SFC4000 has a separate MAC for use at sub-10G speeds. Introduce an efx_mac_operations structure with implementations for the two MACs. Switch between the MACs as necessary. PHY settings are independent of the MAC, so add get_settings() and set_settings() to efx_phy_operations. Also add macs field to indicate which MACs the PHY is connected to. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
375 lines
12 KiB
C
375 lines
12 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/delay.h>
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#include "net_driver.h"
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#include "efx.h"
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#include "falcon.h"
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#include "falcon_hwdefs.h"
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#include "falcon_io.h"
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#include "mac.h"
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#include "mdio_10g.h"
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#include "phy.h"
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#include "boards.h"
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#include "workarounds.h"
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/**************************************************************************
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*
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* MAC operations
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*
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*************************************************************************/
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/* Configure the XAUI driver that is an output from Falcon */
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static void falcon_setup_xaui(struct efx_nic *efx)
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{
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efx_oword_t sdctl, txdrv;
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/* Move the XAUI into low power, unless there is no PHY, in
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* which case the XAUI will have to drive a cable. */
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if (efx->phy_type == PHY_TYPE_NONE)
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return;
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falcon_read(efx, &sdctl, XX_SD_CTL_REG);
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EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_OWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
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falcon_write(efx, &sdctl, XX_SD_CTL_REG);
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EFX_POPULATE_OWORD_8(txdrv,
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XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
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XX_DTXD, XX_TXDRV_DTX_DEFAULT,
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XX_DTXC, XX_TXDRV_DTX_DEFAULT,
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XX_DTXB, XX_TXDRV_DTX_DEFAULT,
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XX_DTXA, XX_TXDRV_DTX_DEFAULT);
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falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG);
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}
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int falcon_reset_xaui(struct efx_nic *efx)
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{
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efx_oword_t reg;
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int count;
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EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
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falcon_write(efx, ®, XX_PWR_RST_REG);
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/* Give some time for the link to establish */
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for (count = 0; count < 1000; count++) { /* wait upto 10ms */
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falcon_read(efx, ®, XX_PWR_RST_REG);
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if (EFX_OWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
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falcon_setup_xaui(efx);
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return 0;
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}
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udelay(10);
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}
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EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
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return -ETIMEDOUT;
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}
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static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
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{
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efx_oword_t reg;
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if ((falcon_rev(efx) != FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
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return;
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/* We expect xgmii faults if the wireside link is up */
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if (!EFX_WORKAROUND_5147(efx) || !efx->link_up)
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return;
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/* We can only use this interrupt to signal the negative edge of
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* xaui_align [we have to poll the positive edge]. */
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if (!efx->mac_up)
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return;
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/* Flush the ISR */
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if (enable)
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falcon_read(efx, ®, XM_MGT_INT_REG_B0);
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EFX_POPULATE_OWORD_2(reg,
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XM_MSK_RMTFLT, !enable,
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XM_MSK_LCLFLT, !enable);
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falcon_write(efx, ®, XM_MGT_INT_MSK_REG_B0);
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}
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/* Get status of XAUI link */
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bool falcon_xaui_link_ok(struct efx_nic *efx)
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{
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efx_oword_t reg;
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bool align_done, link_ok = false;
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int sync_status;
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if (LOOPBACK_INTERNAL(efx))
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return true;
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/* Read link status */
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falcon_read(efx, ®, XX_CORE_STAT_REG);
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align_done = EFX_OWORD_FIELD(reg, XX_ALIGN_DONE);
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sync_status = EFX_OWORD_FIELD(reg, XX_SYNC_STAT);
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if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
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link_ok = true;
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/* Clear link status ready for next read */
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EFX_SET_OWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
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EFX_SET_OWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
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EFX_SET_OWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
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falcon_write(efx, ®, XX_CORE_STAT_REG);
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/* If the link is up, then check the phy side of the xaui link */
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if (efx->link_up && link_ok)
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if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
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link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
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return link_ok;
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}
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static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
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{
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unsigned int max_frame_len;
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efx_oword_t reg;
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bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
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/* Configure MAC - cut-thru mode is hard wired on */
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EFX_POPULATE_DWORD_3(reg,
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XM_RX_JUMBO_MODE, 1,
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XM_TX_STAT_EN, 1,
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XM_RX_STAT_EN, 1);
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falcon_write(efx, ®, XM_GLB_CFG_REG);
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/* Configure TX */
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EFX_POPULATE_DWORD_6(reg,
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XM_TXEN, 1,
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XM_TX_PRMBL, 1,
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XM_AUTO_PAD, 1,
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XM_TXCRC, 1,
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XM_FCNTL, 1,
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XM_IPG, 0x3);
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falcon_write(efx, ®, XM_TX_CFG_REG);
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/* Configure RX */
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EFX_POPULATE_DWORD_5(reg,
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XM_RXEN, 1,
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XM_AUTO_DEPAD, 0,
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XM_ACPT_ALL_MCAST, 1,
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XM_ACPT_ALL_UCAST, efx->promiscuous,
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XM_PASS_CRC_ERR, 1);
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falcon_write(efx, ®, XM_RX_CFG_REG);
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/* Set frame length */
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max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
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EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
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falcon_write(efx, ®, XM_RX_PARAM_REG);
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EFX_POPULATE_DWORD_2(reg,
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XM_MAX_TX_FRM_SIZE, max_frame_len,
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XM_TX_JUMBO_MODE, 1);
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falcon_write(efx, ®, XM_TX_PARAM_REG);
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EFX_POPULATE_DWORD_2(reg,
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XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
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XM_DIS_FCNTL, !rx_fc);
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falcon_write(efx, ®, XM_FC_REG);
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/* Set MAC address */
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EFX_POPULATE_DWORD_4(reg,
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XM_ADR_0, efx->net_dev->dev_addr[0],
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XM_ADR_1, efx->net_dev->dev_addr[1],
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XM_ADR_2, efx->net_dev->dev_addr[2],
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XM_ADR_3, efx->net_dev->dev_addr[3]);
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falcon_write(efx, ®, XM_ADR_LO_REG);
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EFX_POPULATE_DWORD_2(reg,
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XM_ADR_4, efx->net_dev->dev_addr[4],
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XM_ADR_5, efx->net_dev->dev_addr[5]);
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falcon_write(efx, ®, XM_ADR_HI_REG);
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}
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static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
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{
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efx_oword_t reg;
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bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
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bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
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bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
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/* XGXS block is flaky and will need to be reset if moving
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* into our out of XGMII, XGXS or XAUI loopbacks. */
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if (EFX_WORKAROUND_5147(efx)) {
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bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
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bool reset_xgxs;
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falcon_read(efx, ®, XX_CORE_STAT_REG);
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old_xgxs_loopback = EFX_OWORD_FIELD(reg, XX_XGXS_LB_EN);
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old_xgmii_loopback = EFX_OWORD_FIELD(reg, XX_XGMII_LB_EN);
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falcon_read(efx, ®, XX_SD_CTL_REG);
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old_xaui_loopback = EFX_OWORD_FIELD(reg, XX_LPBKA);
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/* The PHY driver may have turned XAUI off */
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reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
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(xaui_loopback != old_xaui_loopback) ||
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(xgmii_loopback != old_xgmii_loopback));
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if (reset_xgxs)
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falcon_reset_xaui(efx);
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}
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falcon_read(efx, ®, XX_CORE_STAT_REG);
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EFX_SET_OWORD_FIELD(reg, XX_FORCE_SIG,
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(xgxs_loopback || xaui_loopback) ?
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XX_FORCE_SIG_DECODE_FORCED : 0);
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EFX_SET_OWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
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EFX_SET_OWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
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falcon_write(efx, ®, XX_CORE_STAT_REG);
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falcon_read(efx, ®, XX_SD_CTL_REG);
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EFX_SET_OWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
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falcon_write(efx, ®, XX_SD_CTL_REG);
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}
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/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
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* to come back up. Bash it until it comes back up */
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static void falcon_check_xaui_link_up(struct efx_nic *efx, int tries)
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{
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efx->mac_up = falcon_xaui_link_ok(efx);
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if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
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efx_phy_mode_disabled(efx->phy_mode))
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/* XAUI link is expected to be down */
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return;
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while (!efx->mac_up && tries) {
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EFX_LOG(efx, "bashing xaui\n");
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falcon_reset_xaui(efx);
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udelay(200);
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efx->mac_up = falcon_xaui_link_ok(efx);
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--tries;
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}
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}
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static void falcon_reconfigure_xmac(struct efx_nic *efx)
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{
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falcon_mask_status_intr(efx, false);
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falcon_reconfigure_xgxs_core(efx);
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falcon_reconfigure_xmac_core(efx);
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falcon_reconfigure_mac_wrapper(efx);
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falcon_check_xaui_link_up(efx, 5);
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falcon_mask_status_intr(efx, true);
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}
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static void falcon_update_stats_xmac(struct efx_nic *efx)
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{
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struct efx_mac_stats *mac_stats = &efx->mac_stats;
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int rc;
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rc = falcon_dma_stats(efx, XgDmaDone_offset);
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if (rc)
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return;
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/* Update MAC stats from DMAed values */
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FALCON_STAT(efx, XgRxOctets, rx_bytes);
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FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
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FALCON_STAT(efx, XgRxPkts, rx_packets);
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FALCON_STAT(efx, XgRxPktsOK, rx_good);
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FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
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FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
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FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
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FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
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FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
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FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
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FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
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FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
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FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
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FALCON_STAT(efx, XgRxAlignError, rx_align_error);
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FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
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FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
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FALCON_STAT(efx, XgRxControlPkts, rx_control);
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FALCON_STAT(efx, XgRxPausePkts, rx_pause);
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FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
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FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
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FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
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FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
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FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
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FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
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FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
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FALCON_STAT(efx, XgRxLengthError, rx_length_error);
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FALCON_STAT(efx, XgTxPkts, tx_packets);
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FALCON_STAT(efx, XgTxOctets, tx_bytes);
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FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
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FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
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FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
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FALCON_STAT(efx, XgTxControlPkts, tx_control);
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FALCON_STAT(efx, XgTxPausePkts, tx_pause);
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FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
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FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
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FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
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FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
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FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
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FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
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FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
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FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
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FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
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FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
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FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
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FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
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/* Update derived statistics */
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mac_stats->tx_good_bytes =
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(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
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mac_stats->tx_control * 64);
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mac_stats->rx_bad_bytes =
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(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
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mac_stats->rx_control * 64);
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}
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static int falcon_check_xmac(struct efx_nic *efx)
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{
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bool xaui_link_ok;
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int rc;
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if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
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efx_phy_mode_disabled(efx->phy_mode))
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return 0;
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falcon_mask_status_intr(efx, false);
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xaui_link_ok = falcon_xaui_link_ok(efx);
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if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
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falcon_reset_xaui(efx);
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/* Call the PHY check_hw routine */
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rc = efx->phy_op->check_hw(efx);
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/* Unmask interrupt if everything was (and still is) ok */
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if (xaui_link_ok && efx->link_up)
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falcon_mask_status_intr(efx, true);
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return rc;
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}
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struct efx_mac_operations falcon_xmac_operations = {
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.reconfigure = falcon_reconfigure_xmac,
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.update_stats = falcon_update_stats_xmac,
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.check_hw = falcon_check_xmac,
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};
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