399fe2bdd3
... for consistency with ppc64 and to make merging easier. Signed-off-by: Paul Mackerras <paulus@samba.org>
794 lines
21 KiB
C
794 lines
21 KiB
C
/*
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* Support for PCI bridges found on Power Macintoshes.
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* At present the "bandit" and "chaos" bridges are supported.
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* Fortunately you access configuration space in the same
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* way with either bridge.
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*
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* Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
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* Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/iommu.h>
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#include <asm/ppc-pci.h>
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#include "pmac.h"
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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/* XXX Could be per-controller, but I don't think we risk anything by
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* assuming we won't have both UniNorth and Bandit */
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static int has_uninorth;
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static struct pci_controller *u3_agp;
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struct device_node *k2_skiplist[2];
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static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
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{
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for (; node != 0;node = node->sibling) {
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int * bus_range;
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unsigned int *class_code;
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int len;
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/* For PCI<->PCI bridges or CardBus bridges, we go down */
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class_code = (unsigned int *) get_property(node, "class-code", NULL);
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if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
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(*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
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continue;
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bus_range = (int *) get_property(node, "bus-range", &len);
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if (bus_range != NULL && len > 2 * sizeof(int)) {
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if (bus_range[1] > higher)
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higher = bus_range[1];
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}
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higher = fixup_one_level_bus_range(node->child, higher);
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}
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return higher;
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}
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/* This routine fixes the "bus-range" property of all bridges in the
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* system since they tend to have their "last" member wrong on macs
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*
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* Note that the bus numbers manipulated here are OF bus numbers, they
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* are not Linux bus numbers.
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*/
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static void __init fixup_bus_range(struct device_node *bridge)
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{
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int * bus_range;
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int len;
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/* Lookup the "bus-range" property for the hose */
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bus_range = (int *) get_property(bridge, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int)) {
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printk(KERN_WARNING "Can't get bus-range for %s\n",
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bridge->full_name);
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return;
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}
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bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
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}
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/*
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* Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
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*
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* The "Bandit" version is present in all early PCI PowerMacs,
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* and up to the first ones using Grackle. Some machines may
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* have 2 bandit controllers (2 PCI busses).
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*
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* "Chaos" is used in some "Bandit"-type machines as a bridge
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* for the separate display bus. It is accessed the same
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* way as bandit, but cannot be probed for devices. It therefore
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* has its own config access functions.
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*
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* The "UniNorth" version is present in all Core99 machines
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* (iBook, G4, new IMacs, and all the recent Apple machines).
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* It contains 3 controllers in one ASIC.
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*
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* The U3 is the bridge used on G5 machines. It contains on
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* AGP bus which is dealt with the old UniNorth access routines
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* and an HyperTransport bus which uses its own set of access
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* functions.
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*/
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#define MACRISC_CFA0(devfn, off) \
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((1 << (unsigned long)PCI_SLOT(dev_fn)) \
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| (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
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| (((unsigned long)(off)) & 0xFCUL))
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#define MACRISC_CFA1(bus, devfn, off) \
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((((unsigned long)(bus)) << 16) \
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|(((unsigned long)(devfn)) << 8) \
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|(((unsigned long)(off)) & 0xFCUL) \
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|1UL)
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static unsigned long macrisc_cfg_access(struct pci_controller* hose,
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u8 bus, u8 dev_fn, u8 offset)
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{
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unsigned int caddr;
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if (bus == hose->first_busno) {
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if (dev_fn < (11 << 3))
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return 0;
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caddr = MACRISC_CFA0(dev_fn, offset);
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} else
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caddr = MACRISC_CFA1(bus, dev_fn, offset);
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/* Uninorth will return garbage if we don't read back the value ! */
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do {
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out_le32(hose->cfg_addr, caddr);
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} while (in_le32(hose->cfg_addr) != caddr);
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offset &= has_uninorth ? 0x07 : 0x03;
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return ((unsigned long)hose->cfg_data) + offset;
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}
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static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8((u8 *)addr);
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break;
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case 2:
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*val = in_le16((u16 *)addr);
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break;
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default:
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*val = in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8((u8 *)addr, val);
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(void) in_8((u8 *)addr);
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break;
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case 2:
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out_le16((u16 *)addr, val);
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(void) in_le16((u16 *)addr);
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break;
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default:
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out_le32((u32 *)addr, val);
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(void) in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops macrisc_pci_ops =
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{
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macrisc_read_config,
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macrisc_write_config
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};
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/*
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* These versions of U3 HyperTransport config space access ops do not
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* implement self-view of the HT host yet
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*/
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/*
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* This function deals with some "special cases" devices.
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*
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* 0 -> No special case
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* 1 -> Skip the device but act as if the access was successfull
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* (return 0xff's on reads, eventually, cache config space
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* accesses in a later version)
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* -1 -> Hide the device (unsuccessful acess)
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*/
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static int u3_ht_skip_device(struct pci_controller *hose,
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struct pci_bus *bus, unsigned int devfn)
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{
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struct device_node *busdn, *dn;
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int i;
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/* We only allow config cycles to devices that are in OF device-tree
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* as we are apparently having some weird things going on with some
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* revs of K2 on recent G5s
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*/
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if (bus->self)
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busdn = pci_device_to_OF_node(bus->self);
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else
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busdn = hose->arch_data;
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for (dn = busdn->child; dn; dn = dn->sibling)
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if (dn->data && PCI_DN(dn)->devfn == devfn)
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break;
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if (dn == NULL)
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return -1;
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/*
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* When a device in K2 is powered down, we die on config
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* cycle accesses. Fix that here.
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*/
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for (i=0; i<2; i++)
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if (k2_skiplist[i] == dn)
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return 1;
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return 0;
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}
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#define U3_HT_CFA0(devfn, off) \
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((((unsigned long)devfn) << 8) | offset)
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#define U3_HT_CFA1(bus, devfn, off) \
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(U3_HT_CFA0(devfn, off) \
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+ (((unsigned long)bus) << 16) \
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+ 0x01000000UL)
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static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
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u8 bus, u8 devfn, u8 offset)
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{
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if (bus == hose->first_busno) {
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/* For now, we don't self probe U3 HT bridge */
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if (PCI_SLOT(devfn) == 0)
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return 0;
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return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
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} else
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return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
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}
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (u3_ht_skip_device(hose, bus, devfn)) {
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case 0:
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break;
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case 1:
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switch (len) {
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case 1:
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*val = 0xff; break;
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case 2:
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*val = 0xffff; break;
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default:
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*val = 0xfffffffful; break;
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}
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return PCIBIOS_SUCCESSFUL;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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*val = in_8((u8 *)addr);
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break;
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case 2:
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*val = in_le16((u16 *)addr);
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break;
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default:
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*val = in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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{
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struct pci_controller *hose;
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unsigned long addr;
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
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if (!addr)
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return PCIBIOS_DEVICE_NOT_FOUND;
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switch (u3_ht_skip_device(hose, bus, devfn)) {
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case 0:
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break;
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case 1:
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return PCIBIOS_SUCCESSFUL;
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default:
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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switch (len) {
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case 1:
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out_8((u8 *)addr, val);
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(void) in_8((u8 *)addr);
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break;
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case 2:
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out_le16((u16 *)addr, val);
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(void) in_le16((u16 *)addr);
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break;
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default:
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out_le32((u32 *)addr, val);
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(void) in_le32((u32 *)addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops u3_ht_pci_ops =
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{
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u3_ht_read_config,
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u3_ht_write_config
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};
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static void __init setup_u3_agp(struct pci_controller* hose)
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{
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/* On G5, we move AGP up to high bus number so we don't need
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* to reassign bus numbers for HT. If we ever have P2P bridges
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* on AGP, we'll have to move pci_assign_all_buses to the
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* pci_controller structure so we enable it for AGP and not for
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* HT childs.
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* We hard code the address because of the different size of
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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*/
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hose->first_busno = 0xf0;
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hose->last_busno = 0xff;
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has_uninorth = 1;
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hose->ops = ¯isc_pci_ops;
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hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
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hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
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u3_agp = hose;
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}
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static void __init setup_u3_ht(struct pci_controller* hose)
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{
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struct device_node *np = (struct device_node *)hose->arch_data;
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int i, cur;
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hose->ops = &u3_ht_pci_ops;
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/* We hard code the address because of the different size of
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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*/
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hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
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/*
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* /ht node doesn't expose a "ranges" property, so we "remove" regions that
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* have been allocated to AGP. So far, this version of the code doesn't assign
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* any of the 0xfxxxxxxx "fine" memory regions to /ht.
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* We need to fix that sooner or later by either parsing all child "ranges"
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* properties or figuring out the U3 address space decoding logic and
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* then read it's configuration register (if any).
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*/
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hose->io_base_phys = 0xf4000000;
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hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
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isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
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hose->io_resource.name = np->full_name;
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hose->io_resource.start = 0;
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hose->io_resource.end = 0x003fffff;
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hose->io_resource.flags = IORESOURCE_IO;
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hose->pci_mem_offset = 0;
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hose->first_busno = 0;
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hose->last_busno = 0xef;
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hose->mem_resources[0].name = np->full_name;
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hose->mem_resources[0].start = 0x80000000;
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hose->mem_resources[0].end = 0xefffffff;
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hose->mem_resources[0].flags = IORESOURCE_MEM;
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if (u3_agp == NULL) {
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DBG("U3 has no AGP, using full resource range\n");
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return;
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}
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/* We "remove" the AGP resources from the resources allocated to HT, that
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* is we create "holes". However, that code does assumptions that so far
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* happen to be true (cross fingers...), typically that resources in the
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* AGP node are properly ordered
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*/
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cur = 0;
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for (i=0; i<3; i++) {
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struct resource *res = &u3_agp->mem_resources[i];
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if (res->flags != IORESOURCE_MEM)
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continue;
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/* We don't care about "fine" resources */
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if (res->start >= 0xf0000000)
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continue;
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/* Check if it's just a matter of "shrinking" us in one direction */
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if (hose->mem_resources[cur].start == res->start) {
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DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
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cur, hose->mem_resources[cur].start, res->end + 1);
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hose->mem_resources[cur].start = res->end + 1;
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continue;
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}
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if (hose->mem_resources[cur].end == res->end) {
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DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
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cur, hose->mem_resources[cur].end, res->start - 1);
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hose->mem_resources[cur].end = res->start - 1;
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continue;
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}
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/* No, it's not the case, we need a hole */
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if (cur == 2) {
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/* not enough resources for a hole, we drop part of the range */
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printk(KERN_WARNING "Running out of resources for /ht host !\n");
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hose->mem_resources[cur].end = res->start - 1;
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continue;
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}
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cur++;
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DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
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cur-1, res->start - 1, cur, res->end + 1);
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hose->mem_resources[cur].name = np->full_name;
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hose->mem_resources[cur].flags = IORESOURCE_MEM;
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hose->mem_resources[cur].start = res->end + 1;
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hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
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hose->mem_resources[cur-1].end = res->start - 1;
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}
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}
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static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary)
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{
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static unsigned int static_lc_ranges[2024];
|
|
unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
|
|
unsigned int size;
|
|
int rlen = 0, orig_rlen;
|
|
int memno = 0;
|
|
struct resource *res;
|
|
int np, na = prom_n_addr_cells(dev);
|
|
|
|
np = na + 5;
|
|
|
|
/* First we try to merge ranges to fix a problem with some pmacs
|
|
* that can have more than 3 ranges, fortunately using contiguous
|
|
* addresses -- BenH
|
|
*/
|
|
dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
|
|
if (!dt_ranges)
|
|
return;
|
|
/* lc_ranges = alloc_bootmem(rlen);*/
|
|
lc_ranges = static_lc_ranges;
|
|
if (!lc_ranges)
|
|
return; /* what can we do here ? */
|
|
memcpy(lc_ranges, dt_ranges, rlen);
|
|
orig_rlen = rlen;
|
|
|
|
/* Let's work on a copy of the "ranges" property instead of damaging
|
|
* the device-tree image in memory
|
|
*/
|
|
ranges = lc_ranges;
|
|
prev = NULL;
|
|
while ((rlen -= np * sizeof(unsigned int)) >= 0) {
|
|
if (prev) {
|
|
if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
|
|
(prev[2] + prev[na+4]) == ranges[2] &&
|
|
(prev[na+2] + prev[na+4]) == ranges[na+2]) {
|
|
prev[na+4] += ranges[na+4];
|
|
ranges[0] = 0;
|
|
ranges += np;
|
|
continue;
|
|
}
|
|
}
|
|
prev = ranges;
|
|
ranges += np;
|
|
}
|
|
|
|
/*
|
|
* The ranges property is laid out as an array of elements,
|
|
* each of which comprises:
|
|
* cells 0 - 2: a PCI address
|
|
* cells 3 or 3+4: a CPU physical address
|
|
* (size depending on dev->n_addr_cells)
|
|
* cells 4+5 or 5+6: the size of the range
|
|
*/
|
|
ranges = lc_ranges;
|
|
rlen = orig_rlen;
|
|
while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
|
|
res = NULL;
|
|
size = ranges[na+4];
|
|
switch (ranges[0] >> 24) {
|
|
case 1: /* I/O space */
|
|
if (ranges[2] != 0)
|
|
break;
|
|
hose->io_base_phys = ranges[na+2];
|
|
/* limit I/O space to 16MB */
|
|
if (size > 0x01000000)
|
|
size = 0x01000000;
|
|
hose->io_base_virt = ioremap(ranges[na+2], size);
|
|
if (primary)
|
|
isa_io_base = (unsigned long) hose->io_base_virt;
|
|
res = &hose->io_resource;
|
|
res->flags = IORESOURCE_IO;
|
|
res->start = ranges[2];
|
|
break;
|
|
case 2: /* memory space */
|
|
memno = 0;
|
|
if (ranges[1] == 0 && ranges[2] == 0
|
|
&& ranges[na+4] <= (16 << 20)) {
|
|
/* 1st 16MB, i.e. ISA memory area */
|
|
#if 0
|
|
if (primary)
|
|
isa_mem_base = ranges[na+2];
|
|
#endif
|
|
memno = 1;
|
|
}
|
|
while (memno < 3 && hose->mem_resources[memno].flags)
|
|
++memno;
|
|
if (memno == 0)
|
|
hose->pci_mem_offset = ranges[na+2] - ranges[2];
|
|
if (memno < 3) {
|
|
res = &hose->mem_resources[memno];
|
|
res->flags = IORESOURCE_MEM;
|
|
res->start = ranges[na+2];
|
|
}
|
|
break;
|
|
}
|
|
if (res != NULL) {
|
|
res->name = dev->full_name;
|
|
res->end = res->start + size - 1;
|
|
res->parent = NULL;
|
|
res->sibling = NULL;
|
|
res->child = NULL;
|
|
}
|
|
ranges += np;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* We assume that if we have a G3 powermac, we have one bridge called
|
|
* "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
|
|
* if we have one or more bandit or chaos bridges, we don't have a MPC106.
|
|
*/
|
|
static int __init add_bridge(struct device_node *dev)
|
|
{
|
|
int len;
|
|
struct pci_controller *hose;
|
|
char* disp_name;
|
|
int *bus_range;
|
|
int primary = 1;
|
|
struct property *of_prop;
|
|
|
|
DBG("Adding PCI host bridge %s\n", dev->full_name);
|
|
|
|
bus_range = (int *) get_property(dev, "bus-range", &len);
|
|
if (bus_range == NULL || len < 2 * sizeof(int)) {
|
|
printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
|
|
dev->full_name);
|
|
}
|
|
|
|
hose = alloc_bootmem(sizeof(struct pci_controller));
|
|
if (hose == NULL)
|
|
return -ENOMEM;
|
|
pci_setup_pci_controller(hose);
|
|
|
|
hose->arch_data = dev;
|
|
hose->first_busno = bus_range ? bus_range[0] : 0;
|
|
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
|
|
|
of_prop = alloc_bootmem(sizeof(struct property) +
|
|
sizeof(hose->global_number));
|
|
if (of_prop) {
|
|
memset(of_prop, 0, sizeof(struct property));
|
|
of_prop->name = "linux,pci-domain";
|
|
of_prop->length = sizeof(hose->global_number);
|
|
of_prop->value = (unsigned char *)&of_prop[1];
|
|
memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number));
|
|
prom_add_property(dev, of_prop);
|
|
}
|
|
|
|
disp_name = NULL;
|
|
if (device_is_compatible(dev, "u3-agp")) {
|
|
setup_u3_agp(hose);
|
|
disp_name = "U3-AGP";
|
|
primary = 0;
|
|
} else if (device_is_compatible(dev, "u3-ht")) {
|
|
setup_u3_ht(hose);
|
|
disp_name = "U3-HT";
|
|
primary = 1;
|
|
}
|
|
printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
|
|
disp_name, hose->first_busno, hose->last_busno);
|
|
|
|
/* Interpret the "ranges" property */
|
|
/* This also maps the I/O region and sets isa_io/mem_base */
|
|
pmac_process_bridge_OF_ranges(hose, dev, primary);
|
|
|
|
/* Fixup "bus-range" OF property */
|
|
fixup_bus_range(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* We use our own read_irq_line here because PCI_INTERRUPT_PIN is
|
|
* crap on some of Apple ASICs. We unconditionally use the Open Firmware
|
|
* interrupt number as this is always right.
|
|
*/
|
|
static int pmac_pci_read_irq_line(struct pci_dev *pci_dev)
|
|
{
|
|
struct device_node *node;
|
|
|
|
node = pci_device_to_OF_node(pci_dev);
|
|
if (node == NULL)
|
|
return -1;
|
|
if (node->n_intrs == 0)
|
|
return -1;
|
|
pci_dev->irq = node->intrs[0].line;
|
|
pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init pmac_pcibios_fixup(void)
|
|
{
|
|
struct pci_dev *dev = NULL;
|
|
|
|
for_each_pci_dev(dev)
|
|
pmac_pci_read_irq_line(dev);
|
|
}
|
|
|
|
static void __init pmac_fixup_phb_resources(void)
|
|
{
|
|
struct pci_controller *hose, *tmp;
|
|
|
|
list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
|
|
unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
|
|
hose->io_resource.start += offset;
|
|
hose->io_resource.end += offset;
|
|
printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
|
|
hose->global_number,
|
|
hose->io_resource.start, hose->io_resource.end);
|
|
}
|
|
}
|
|
|
|
void __init pmac_pci_init(void)
|
|
{
|
|
struct device_node *np, *root;
|
|
struct device_node *ht = NULL;
|
|
|
|
/* Probe root PCI hosts, that is on U3 the AGP host and the
|
|
* HyperTransport host. That one is actually "kept" around
|
|
* and actually added last as it's resource management relies
|
|
* on the AGP resources to have been setup first
|
|
*/
|
|
root = of_find_node_by_path("/");
|
|
if (root == NULL) {
|
|
printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
|
|
return;
|
|
}
|
|
for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
|
|
if (np->name == NULL)
|
|
continue;
|
|
if (strcmp(np->name, "pci") == 0) {
|
|
if (add_bridge(np) == 0)
|
|
of_node_get(np);
|
|
}
|
|
if (strcmp(np->name, "ht") == 0) {
|
|
of_node_get(np);
|
|
ht = np;
|
|
}
|
|
}
|
|
of_node_put(root);
|
|
|
|
/* Now setup the HyperTransport host if we found any
|
|
*/
|
|
if (ht && add_bridge(ht) != 0)
|
|
of_node_put(ht);
|
|
|
|
/* Fixup the IO resources on our host bridges as the common code
|
|
* does it only for childs of the host bridges
|
|
*/
|
|
pmac_fixup_phb_resources();
|
|
|
|
/* Setup the linkage between OF nodes and PHBs */
|
|
pci_devs_phb_init();
|
|
|
|
/* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
|
|
* assume there is no P2P bridge on the AGP bus, which should be a
|
|
* safe assumptions hopefully.
|
|
*/
|
|
if (u3_agp) {
|
|
struct device_node *np = u3_agp->arch_data;
|
|
PCI_DN(np)->busno = 0xf0;
|
|
for (np = np->child; np; np = np->sibling)
|
|
PCI_DN(np)->busno = 0xf0;
|
|
}
|
|
|
|
pmac_check_ht_link();
|
|
|
|
/* Tell pci.c to not use the common resource allocation mecanism */
|
|
pci_probe_only = 1;
|
|
|
|
/* Allow all IO */
|
|
io_page_mask = -1;
|
|
}
|
|
|
|
/*
|
|
* Disable second function on K2-SATA, it's broken
|
|
* and disable IO BARs on first one
|
|
*/
|
|
static void fixup_k2_sata(struct pci_dev* dev)
|
|
{
|
|
int i;
|
|
u16 cmd;
|
|
|
|
if (PCI_FUNC(dev->devfn) > 0) {
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
for (i = 0; i < 6; i++) {
|
|
dev->resource[i].start = dev->resource[i].end = 0;
|
|
dev->resource[i].flags = 0;
|
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
|
|
}
|
|
} else {
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
cmd &= ~PCI_COMMAND_IO;
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
for (i = 0; i < 5; i++) {
|
|
dev->resource[i].start = dev->resource[i].end = 0;
|
|
dev->resource[i].flags = 0;
|
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
|
|
}
|
|
}
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);
|
|
|