190de00538
This reworks the boot wrapper library function that probes the chip clocks. Better separate the base function that is used on 440GX,SPe,EP,... from the uart fixups as those need different device-tree path on different processors. Also, rework the function itself based on the arch/ppc code from Eugene Surovegin which I find more readable, and which handles one more bypass case. Also handle the subtle difference between 440EP/EPx and 440SPe/GX, on the former, PerClk is derived from the PLB clock while on the later, it's derived from the OPB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
195 lines
6.0 KiB
C
195 lines
6.0 KiB
C
#ifndef _PPC_BOOT_DCR_H_
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#define _PPC_BOOT_DCR_H_
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#define mfdcr(rn) \
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({ \
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unsigned long rval; \
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asm volatile("mfdcr %0,%1" : "=r"(rval) : "i"(rn)); \
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rval; \
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})
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#define mtdcr(rn, val) \
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asm volatile("mtdcr %0,%1" : : "i"(rn), "r"(val))
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/* 440GP/440GX SDRAM controller DCRs */
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#define DCRN_SDRAM0_CFGADDR 0x010
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#define DCRN_SDRAM0_CFGDATA 0x011
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#define SDRAM0_READ(offset) ({\
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mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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mfdcr(DCRN_SDRAM0_CFGDATA); })
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#define SDRAM0_WRITE(offset, data) ({\
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mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
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mtdcr(DCRN_SDRAM0_CFGDATA, data); })
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#define SDRAM0_B0CR 0x40
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#define SDRAM0_B1CR 0x44
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#define SDRAM0_B2CR 0x48
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#define SDRAM0_B3CR 0x4c
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static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR,
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SDRAM0_B2CR, SDRAM0_B3CR };
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#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
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#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
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#define SDRAM_CONFIG_BANK_SIZE(reg) \
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(0x00400000 << ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17))
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/* 440GP External Bus Controller (EBC) */
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#define DCRN_EBC0_CFGADDR 0x012
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#define DCRN_EBC0_CFGDATA 0x013
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#define EBC_NUM_BANKS 8
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#define EBC_B0CR 0x00
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#define EBC_B1CR 0x01
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#define EBC_B2CR 0x02
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#define EBC_B3CR 0x03
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#define EBC_B4CR 0x04
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#define EBC_B5CR 0x05
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#define EBC_B6CR 0x06
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#define EBC_B7CR 0x07
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#define EBC_BXCR(n) (n)
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#define EBC_BXCR_BAS 0xfff00000
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#define EBC_BXCR_BS 0x000e0000
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#define EBC_BXCR_BANK_SIZE(reg) \
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(0x100000 << (((reg) & EBC_BXCR_BS) >> 17))
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#define EBC_BXCR_BU 0x00018000
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#define EBC_BXCR_BU_OFF 0x00000000
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#define EBC_BXCR_BU_RO 0x00008000
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#define EBC_BXCR_BU_WO 0x00010000
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#define EBC_BXCR_BU_RW 0x00018000
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#define EBC_BXCR_BW 0x00006000
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#define EBC_B0AP 0x10
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#define EBC_B1AP 0x11
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#define EBC_B2AP 0x12
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#define EBC_B3AP 0x13
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#define EBC_B4AP 0x14
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#define EBC_B5AP 0x15
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#define EBC_B6AP 0x16
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#define EBC_B7AP 0x17
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#define EBC_BXAP(n) (0x10+(n))
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#define EBC_BEAR 0x20
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#define EBC_BESR 0x21
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#define EBC_CFG 0x23
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#define EBC_CID 0x24
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/* 440GP Clock, PM, chip control */
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#define DCRN_CPC0_SR 0x0b0
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#define DCRN_CPC0_ER 0x0b1
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#define DCRN_CPC0_FR 0x0b2
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#define DCRN_CPC0_SYS0 0x0e0
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#define CPC0_SYS0_TUNE 0xffc00000
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#define CPC0_SYS0_FBDV_MASK 0x003c0000
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#define CPC0_SYS0_FWDVA_MASK 0x00038000
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#define CPC0_SYS0_FWDVB_MASK 0x00007000
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#define CPC0_SYS0_OPDV_MASK 0x00000c00
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#define CPC0_SYS0_EPDV_MASK 0x00000300
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/* Helper macros to compute the actual clock divider values from the
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* encodings in the CPC0 register */
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#define CPC0_SYS0_FBDV(reg) \
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((((((reg) & CPC0_SYS0_FBDV_MASK) >> 18) - 1) & 0xf) + 1)
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#define CPC0_SYS0_FWDVA(reg) \
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(8 - (((reg) & CPC0_SYS0_FWDVA_MASK) >> 15))
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#define CPC0_SYS0_FWDVB(reg) \
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(8 - (((reg) & CPC0_SYS0_FWDVB_MASK) >> 12))
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#define CPC0_SYS0_OPDV(reg) \
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((((reg) & CPC0_SYS0_OPDV_MASK) >> 10) + 1)
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#define CPC0_SYS0_EPDV(reg) \
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((((reg) & CPC0_SYS0_EPDV_MASK) >> 8) + 1)
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#define CPC0_SYS0_EXTSL 0x00000080
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#define CPC0_SYS0_RW_MASK 0x00000060
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#define CPC0_SYS0_RL 0x00000010
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#define CPC0_SYS0_ZMIISL_MASK 0x0000000c
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#define CPC0_SYS0_BYPASS 0x00000002
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#define CPC0_SYS0_NTO1 0x00000001
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#define DCRN_CPC0_SYS1 0x0e1
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#define DCRN_CPC0_CUST0 0x0e2
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#define DCRN_CPC0_CUST1 0x0e3
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#define DCRN_CPC0_STRP0 0x0e4
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#define DCRN_CPC0_STRP1 0x0e5
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#define DCRN_CPC0_STRP2 0x0e6
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#define DCRN_CPC0_STRP3 0x0e7
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#define DCRN_CPC0_GPIO 0x0e8
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#define DCRN_CPC0_PLB 0x0e9
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#define DCRN_CPC0_CR1 0x0ea
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#define DCRN_CPC0_CR0 0x0eb
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#define CPC0_CR0_SWE 0x80000000
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#define CPC0_CR0_CETE 0x40000000
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#define CPC0_CR0_U1FCS 0x20000000
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#define CPC0_CR0_U0DTE 0x10000000
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#define CPC0_CR0_U0DRE 0x08000000
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#define CPC0_CR0_U0DC 0x04000000
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#define CPC0_CR0_U1DTE 0x02000000
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#define CPC0_CR0_U1DRE 0x01000000
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#define CPC0_CR0_U1DC 0x00800000
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#define CPC0_CR0_U0EC 0x00400000
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#define CPC0_CR0_U1EC 0x00200000
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#define CPC0_CR0_UDIV_MASK 0x001f0000
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#define CPC0_CR0_UDIV(reg) \
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((((reg) & CPC0_CR0_UDIV_MASK) >> 16) + 1)
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#define DCRN_CPC0_MIRQ0 0x0ec
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#define DCRN_CPC0_MIRQ1 0x0ed
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#define DCRN_CPC0_JTAGID 0x0ef
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#define DCRN_MAL0_CFG 0x180
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#define MAL_RESET 0x80000000
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/* 440EP Clock/Power-on Reset regs */
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#define DCRN_CPR0_ADDR 0xc
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#define DCRN_CPR0_DATA 0xd
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#define CPR0_PLLD0 0x60
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#define CPR0_OPBD0 0xc0
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#define CPR0_PERD0 0xe0
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#define CPR0_PRIMBD0 0xa0
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#define CPR0_SCPID 0x120
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#define CPR0_PLLC0 0x40
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/* 405GP Clocking/Power Management/Chip Control regs */
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#define DCRN_CPC0_PLLMR 0xb0
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#define DCRN_405_CPC0_CR0 0xb1
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#define DCRN_405_CPC0_CR1 0xb2
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/* 440GX Clock control etc */
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#define DCRN_CPR0_CLKUPD 0x020
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#define DCRN_CPR0_PLLC 0x040
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#define DCRN_CPR0_PLLD 0x060
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#define DCRN_CPR0_PRIMAD 0x080
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#define DCRN_CPR0_PRIMBD 0x0a0
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#define DCRN_CPR0_OPBD 0x0c0
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#define DCRN_CPR0_PERD 0x0e0
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#define DCRN_CPR0_MALD 0x100
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#define DCRN_SDR0_CONFIG_ADDR 0xe
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#define DCRN_SDR0_CONFIG_DATA 0xf
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/* SDR read/write helper macros */
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#define SDR0_READ(offset) ({\
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mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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mfdcr(DCRN_SDR0_CONFIG_DATA); })
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#define SDR0_WRITE(offset, data) ({\
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mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
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mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
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#define DCRN_SDR0_UART0 0x0120
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#define DCRN_SDR0_UART1 0x0121
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#define DCRN_SDR0_UART2 0x0122
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#define DCRN_SDR0_UART3 0x0123
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/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */
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#define DCRN_CPR0_CFGADDR 0xc
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#define DCRN_CPR0_CFGDATA 0xd
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#define CPR0_READ(offset) ({\
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mtdcr(DCRN_CPR0_CFGADDR, offset); \
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mfdcr(DCRN_CPR0_CFGDATA); })
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#define CPR0_WRITE(offset, data) ({\
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mtdcr(DCRN_CPR0_CFGADDR, offset); \
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mtdcr(DCRN_CPR0_CFGDATA, data); })
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#endif /* _PPC_BOOT_DCR_H_ */
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