1946d6ef9d
Currently, whenever an erratum workaround is enabled, it will be applied whether or not the erratum is relevent for the CPU. This patch changes this - we check the variant and revision fields in the main ID register to determine which errata to apply. We also avoid re-applying erratum 460075 if it has already been applied. Applying this fix in non-secure mode results in the kernel failing to boot (or even do anything.) This fixes booting on some ARMv7 based platforms which otherwise silently fail. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
307 lines
7.4 KiB
ArmAsm
307 lines
7.4 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#define TTB_C (1 << 0)
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#define TTB_S (1 << 1)
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#define TTB_RGN_NC (0 << 3)
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#define TTB_RGN_OC_WBWA (1 << 3)
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#define TTB_RGN_OC_WT (2 << 3)
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#define TTB_RGN_OC_WB (3 << 3)
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#ifndef CONFIG_SMP
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#define TTB_FLAGS TTB_C|TTB_RGN_OC_WB @ mark PTWs cacheable, outer WB
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#else
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#define TTB_FLAGS TTB_C|TTB_S|TTB_RGN_OC_WBWA @ mark PTWs cacheable and shared, outer WBWA
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#endif
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENDPROC(cpu_v7_proc_init)
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ENTRY(cpu_v7_proc_fin)
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mov pc, lr
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ENDPROC(cpu_v7_proc_fin)
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* It is assumed that:
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*/
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.align 5
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ENTRY(cpu_v7_reset)
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mov pc, r0
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ENDPROC(cpu_v7_reset)
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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dsb @ WFI may enter a low-power mode
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wfi
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mov pc, lr
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ENDPROC(cpu_v7_do_idle)
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ENTRY(cpu_v7_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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dcache_line_size r2, r3
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 1b
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dsb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_dcache_clean_area)
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/*
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* cpu_v7_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys
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*
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* - pgd_phys - physical address of new TTB
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*
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* It is assumed that:
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* - we are not using split page tables
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*/
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ENTRY(cpu_v7_switch_mm)
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#ifdef CONFIG_MMU
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mov r2, #0
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ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
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orr r0, r0, #TTB_FLAGS
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#ifdef CONFIG_ARM_ERRATA_430973
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mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
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#endif
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mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
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isb
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1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
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isb
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mcr p15, 0, r1, c13, c0, 1 @ set context ID
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isb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_switch_mm)
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/*
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* cpu_v7_set_pte_ext(ptep, pte)
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*
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* Set a level 2 translation table entry.
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*
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* - ptep - pointer to level 2 translation table entry
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* (hardware version is stored at -1024 bytes)
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* - pte - PTE value to store
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* - ext - value for extended PTE bits
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*/
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ENTRY(cpu_v7_set_pte_ext)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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bic r3, r1, #0x000003f0
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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tst r1, #1 << 4
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orrne r3, r3, #PTE_EXT_TEX(1)
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tst r1, #L_PTE_WRITE
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tstne r1, #L_PTE_DIRTY
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orreq r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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tstne r3, #PTE_EXT_APX
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bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
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tst r1, #L_PTE_EXEC
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orreq r3, r3, #PTE_EXT_XN
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_set_pte_ext)
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cpu_v7_name:
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.ascii "ARMv7 Processor"
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.align
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__INIT
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/*
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* __v7_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv7 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v7_setup:
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#ifdef CONFIG_SMP
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mrc p15, 0, r0, c1, c0, 1 @ Enable SMP/nAMP mode
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orr r0, r0, #(0x1 << 6)
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mcr p15, 0, r0, c1, c0, 1
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#endif
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r10, r0, #0xff000000 @ ARM?
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teq r10, #0x41000000
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bne 2f
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and r5, r0, #0x00f00000 @ variant
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and r6, r0, #0x0000000f @ revision
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orr r0, r6, r5, lsr #20-4 @ combine variant and revision
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#ifdef CONFIG_ARM_ERRATA_430973
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teq r5, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r0, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r0, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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2: mov r10, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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dsb
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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mcr p15, 0, r10, c2, c0, 2 @ TTB control register
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orr r4, r4, #TTB_FLAGS
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mcr p15, 0, r4, c2, c0, 1 @ load TTB1
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mov r10, #0x1f @ domains 0, 1 = manager
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mcr p15, 0, r10, c3, c0, 0 @ load domain access register
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#endif
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ldr r5, =0xff0aa1a8
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ldr r6, =0x40e040e0
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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mov pc, lr @ return to head.S:__ret
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ENDPROC(__v7_setup)
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/* AT
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* TFR EV X F I D LR
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* .EEE ..EE PUI. .T.T 4RVI ZFRS BLDP WCAM
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* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
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* 1 0 110 0011 1.00 .111 1101 < we want
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*/
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.type v7_crval, #object
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v7_crval:
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crval clear=0x0120c302, mmuset=0x10c0387d, ucset=0x00c0187c
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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.type v7_processor_functions, #object
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ENTRY(v7_processor_functions)
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.word v7_early_abort
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.word pabort_ifar
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.word cpu_v7_proc_init
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.word cpu_v7_proc_fin
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.word cpu_v7_reset
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.word cpu_v7_do_idle
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.word cpu_v7_dcache_clean_area
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.word cpu_v7_switch_mm
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.word cpu_v7_set_pte_ext
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.size v7_processor_functions, . - v7_processor_functions
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv7"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v7"
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.size cpu_elf_name, . - cpu_elf_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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/*
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* Match any ARMv7 processor core.
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*/
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.type __v7_proc_info, #object
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__v7_proc_info:
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Mask for ID
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_SECT_XN | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __v7_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
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.long cpu_v7_name
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.long v7_processor_functions
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.long v7wbi_tlb_fns
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.long v6_user_fns
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.long v7_cache_fns
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.size __v7_proc_info, . - __v7_proc_info
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