3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
215 lines
6.8 KiB
C
215 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef MDSS_DSI_PLL_8996_H
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#define MDSS_DSI_PLL_8996_H
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#define DSIPHY_CMN_CLK_CFG0 0x0010
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#define DSIPHY_CMN_CLK_CFG1 0x0014
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#define DSIPHY_CMN_GLBL_TEST_CTRL 0x0018
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#define DSIPHY_CMN_PLL_CNTRL 0x0048
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#define DSIPHY_CMN_CTRL_0 0x001c
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#define DSIPHY_CMN_CTRL_1 0x0020
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#define DSIPHY_CMN_LDO_CNTRL 0x004c
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#define DSIPHY_PLL_IE_TRIM 0x0400
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#define DSIPHY_PLL_IP_TRIM 0x0404
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#define DSIPHY_PLL_IPTAT_TRIM 0x0410
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#define DSIPHY_PLL_CLKBUFLR_EN 0x041c
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#define DSIPHY_PLL_SYSCLK_EN_RESET 0x0428
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#define DSIPHY_PLL_RESETSM_CNTRL 0x042c
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#define DSIPHY_PLL_RESETSM_CNTRL2 0x0430
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#define DSIPHY_PLL_RESETSM_CNTRL3 0x0434
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#define DSIPHY_PLL_RESETSM_CNTRL4 0x0438
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#define DSIPHY_PLL_RESETSM_CNTRL5 0x043c
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#define DSIPHY_PLL_KVCO_DIV_REF1 0x0440
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#define DSIPHY_PLL_KVCO_DIV_REF2 0x0444
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#define DSIPHY_PLL_KVCO_COUNT1 0x0448
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#define DSIPHY_PLL_KVCO_COUNT2 0x044c
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#define DSIPHY_PLL_VREF_CFG1 0x045c
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#define DSIPHY_PLL_KVCO_CODE 0x0458
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#define DSIPHY_PLL_VCO_DIV_REF1 0x046c
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#define DSIPHY_PLL_VCO_DIV_REF2 0x0470
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#define DSIPHY_PLL_VCO_COUNT1 0x0474
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#define DSIPHY_PLL_VCO_COUNT2 0x0478
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#define DSIPHY_PLL_PLLLOCK_CMP1 0x047c
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#define DSIPHY_PLL_PLLLOCK_CMP2 0x0480
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#define DSIPHY_PLL_PLLLOCK_CMP3 0x0484
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#define DSIPHY_PLL_PLLLOCK_CMP_EN 0x0488
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#define DSIPHY_PLL_PLL_VCO_TUNE 0x048C
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#define DSIPHY_PLL_DEC_START 0x0490
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#define DSIPHY_PLL_SSC_EN_CENTER 0x0494
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#define DSIPHY_PLL_SSC_ADJ_PER1 0x0498
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#define DSIPHY_PLL_SSC_ADJ_PER2 0x049c
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#define DSIPHY_PLL_SSC_PER1 0x04a0
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#define DSIPHY_PLL_SSC_PER2 0x04a4
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#define DSIPHY_PLL_SSC_STEP_SIZE1 0x04a8
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#define DSIPHY_PLL_SSC_STEP_SIZE2 0x04ac
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#define DSIPHY_PLL_DIV_FRAC_START1 0x04b4
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#define DSIPHY_PLL_DIV_FRAC_START2 0x04b8
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#define DSIPHY_PLL_DIV_FRAC_START3 0x04bc
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#define DSIPHY_PLL_TXCLK_EN 0x04c0
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#define DSIPHY_PLL_PLL_CRCTRL 0x04c4
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#define DSIPHY_PLL_RESET_SM_READY_STATUS 0x04cc
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#define DSIPHY_PLL_PLL_MISC1 0x04e8
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#define DSIPHY_PLL_CP_SET_CUR 0x04f0
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#define DSIPHY_PLL_PLL_ICPMSET 0x04f4
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#define DSIPHY_PLL_PLL_ICPCSET 0x04f8
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#define DSIPHY_PLL_PLL_ICP_SET 0x04fc
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#define DSIPHY_PLL_PLL_LPF1 0x0500
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#define DSIPHY_PLL_PLL_LPF2_POSTDIV 0x0504
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#define DSIPHY_PLL_PLL_BANDGAP 0x0508
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL15 0x050
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL19 0x060
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL20 0x064
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL21 0x068
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL22 0x06C
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL23 0x070
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL24 0x074
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL25 0x078
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL26 0x07C
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL27 0x080
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL28 0x084
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#define DSI_DYNAMIC_REFRESH_PLL_CTRL29 0x088
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#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR 0x094
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#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 0x098
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struct dsi_pll_input {
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u32 fref; /* 19.2 Mhz, reference clk */
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u32 fdata; /* bit clock rate */
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u32 dsiclk_sel; /* 1, reg: 0x0014 */
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u32 n2div; /* 1, reg: 0x0010, bit 4-7 */
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u32 ssc_en; /* 1, reg: 0x0494, bit 0 */
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u32 ldo_en; /* 0, reg: 0x004c, bit 0 */
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/* fixed */
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u32 refclk_dbler_en; /* 0, reg: 0x04c0, bit 1 */
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u32 vco_measure_time; /* 5, unknown */
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u32 kvco_measure_time; /* 5, unknown */
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u32 bandgap_timer; /* 4, reg: 0x0430, bit 3 - 5 */
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u32 pll_wakeup_timer; /* 5, reg: 0x043c, bit 0 - 2 */
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u32 plllock_cnt; /* 1, reg: 0x0488, bit 1 - 2 */
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u32 plllock_rng; /* 1, reg: 0x0488, bit 3 - 4 */
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u32 ssc_center; /* 0, reg: 0x0494, bit 1 */
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u32 ssc_adj_period; /* 37, reg: 0x498, bit 0 - 9 */
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u32 ssc_spread; /* 0.005 */
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u32 ssc_freq; /* unknown */
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u32 pll_ie_trim; /* 4, reg: 0x0400 */
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u32 pll_ip_trim; /* 4, reg: 0x0404 */
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u32 pll_iptat_trim; /* reg: 0x0410 */
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u32 pll_cpcset_cur; /* 1, reg: 0x04f0, bit 0 - 2 */
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u32 pll_cpmset_cur; /* 1, reg: 0x04f0, bit 3 - 5 */
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u32 pll_icpmset; /* 4, reg: 0x04fc, bit 3 - 5 */
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u32 pll_icpcset; /* 4, reg: 0x04fc, bit 0 - 2 */
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u32 pll_icpmset_p; /* 0, reg: 0x04f4, bit 0 - 2 */
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u32 pll_icpmset_m; /* 0, reg: 0x04f4, bit 3 - 5 */
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u32 pll_icpcset_p; /* 0, reg: 0x04f8, bit 0 - 2 */
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u32 pll_icpcset_m; /* 0, reg: 0x04f8, bit 3 - 5 */
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u32 pll_lpf_res1; /* 3, reg: 0x0504, bit 0 - 3 */
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u32 pll_lpf_cap1; /* 11, reg: 0x0500, bit 0 - 3 */
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u32 pll_lpf_cap2; /* 1, reg: 0x0500, bit 4 - 7 */
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u32 pll_c3ctrl; /* 2, reg: 0x04c4 */
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u32 pll_r3ctrl; /* 1, reg: 0x04c4 */
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};
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struct dsi_pll_output {
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u32 pll_txclk_en; /* reg: 0x04c0 */
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u32 dec_start; /* reg: 0x0490 */
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u32 div_frac_start; /* reg: 0x04b4, 0x4b8, 0x04bc */
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u32 ssc_period; /* reg: 0x04a0, 0x04a4 */
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u32 ssc_step_size; /* reg: 0x04a8, 0x04ac */
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u32 plllock_cmp; /* reg: 0x047c, 0x0480, 0x0484 */
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u32 pll_vco_div_ref; /* reg: 0x046c, 0x0470 */
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u32 pll_vco_count; /* reg: 0x0474, 0x0478 */
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u32 pll_kvco_div_ref; /* reg: 0x0440, 0x0444 */
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u32 pll_kvco_count; /* reg: 0x0448, 0x044c */
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u32 pll_misc1; /* reg: 0x04e8 */
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u32 pll_lpf2_postdiv; /* reg: 0x0504 */
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u32 pll_resetsm_cntrl; /* reg: 0x042c */
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u32 pll_resetsm_cntrl2; /* reg: 0x0430 */
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u32 pll_resetsm_cntrl5; /* reg: 0x043c */
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u32 pll_kvco_code; /* reg: 0x0458 */
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u32 cmn_clk_cfg0; /* reg: 0x0010 */
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u32 cmn_clk_cfg1; /* reg: 0x0014 */
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u32 cmn_ldo_cntrl; /* reg: 0x004c */
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u32 pll_postdiv; /* vco */
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u32 pll_n1div; /* vco */
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u32 pll_n2div; /* hr_oclk3, pixel */
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u32 fcvo;
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};
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enum {
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DSI_PLL_0,
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DSI_PLL_1,
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DSI_PLL_NUM
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};
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struct dsi_pll_db {
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struct dsi_pll_db *next;
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struct mdss_pll_resources *pll;
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struct dsi_pll_input in;
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struct dsi_pll_output out;
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int source_setup_done;
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};
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enum {
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PLL_OUTPUT_NONE,
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PLL_OUTPUT_RIGHT,
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PLL_OUTPUT_LEFT,
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PLL_OUTPUT_BOTH
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};
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enum {
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PLL_SOURCE_FROM_LEFT,
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PLL_SOURCE_FROM_RIGHT
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};
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enum {
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PLL_UNKNOWN,
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PLL_STANDALONE,
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PLL_SLAVE,
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PLL_MASTER
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};
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int pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
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long pll_vco_round_rate_8996(struct clk *c, unsigned long rate);
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enum handoff pll_vco_handoff_8996(struct clk *c);
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enum handoff shadow_pll_vco_handoff_8996(struct clk *c);
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int shadow_post_n1_div_set_div(struct div_clk *clk, int div);
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int shadow_post_n1_div_get_div(struct div_clk *clk);
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int shadow_n2_div_set_div(struct div_clk *clk, int div);
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int shadow_n2_div_get_div(struct div_clk *clk);
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int shadow_pll_vco_set_rate_8996(struct clk *c, unsigned long rate);
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int pll_vco_prepare_8996(struct clk *c);
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void pll_vco_unprepare_8996(struct clk *c);
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int set_mdss_byte_mux_sel_8996(struct mux_clk *clk, int sel);
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int get_mdss_byte_mux_sel_8996(struct mux_clk *clk);
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int set_mdss_pixel_mux_sel_8996(struct mux_clk *clk, int sel);
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int get_mdss_pixel_mux_sel_8996(struct mux_clk *clk);
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int post_n1_div_set_div(struct div_clk *clk, int div);
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int post_n1_div_get_div(struct div_clk *clk);
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int n2_div_set_div(struct div_clk *clk, int div);
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int n2_div_get_div(struct div_clk *clk);
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int dsi_pll_enable_seq_8996(struct mdss_pll_resources *pll);
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#endif /* MDSS_DSI_PLL_8996_H */
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