0c4661698c
8xx has not had WRITETHRU due to lack of bits in the pte. After the recent rewrite of the 8xx TLB code, there are two bits left. Use one of them to WRITETHRU. Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE? Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
68 lines
3.0 KiB
C
68 lines
3.0 KiB
C
#ifndef _ASM_POWERPC_PTE_8xx_H
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#define _ASM_POWERPC_PTE_8xx_H
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#ifdef __KERNEL__
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/*
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* The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
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* We also use the two level tables, but we can put the real bits in them
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* needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
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* Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
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* additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
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* based upon user/super access. The TLB does not have accessed nor write
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* protect. We assume that if the TLB get loaded with an entry it is
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* accessed, and overload the changed bit for write protect. We use
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* two bits in the software pte that are supposed to be set to zero in
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* the TLB entry (24 and 25) for these indicators. Although the level 1
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* descriptor contains the guarded and writethrough/copyback bits, we can
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* set these at the page level since they get copied from the Mx_TWC
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* register when the TLB entry is loaded. We will use bit 27 for guard, since
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* that is where it exists in the MD_TWC, and bit 26 for writethrough.
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* These will get masked from the level 2 descriptor at TLB load time, and
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* copied to the MD_TWC before it gets loaded.
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* Large page sizes added. We currently support two sizes, 4K and 8M.
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* This also allows a TLB hander optimization because we can directly
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* load the PMD into MD_TWC. The 8M pages are only used for kernel
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* mapping of well known areas. The PMD (PGD) entries contain control
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* flags in addition to the address, so care must be taken that the
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* software no longer assumes these are only pointers.
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*/
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/* Definitions for 8xx embedded chips. */
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#define _PAGE_PRESENT 0x0001 /* Page is valid */
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#define _PAGE_FILE 0x0002 /* when !present: nonlinear file mapping */
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#define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
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#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
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#define _PAGE_SPECIAL 0x0008 /* SW entry, forced to 0 by the TLB miss */
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#define _PAGE_DIRTY 0x0100 /* C: page changed */
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/* These 4 software bits must be masked out when the entry is loaded
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* into the TLB, 1 SW bit left(0x0080).
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*/
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#define _PAGE_GUARDED 0x0010 /* software: guarded access */
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#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
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#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */
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/* Setting any bits in the nibble with the follow two controls will
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* require a TLB exception handler change. It is assumed unused bits
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* are always zero.
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*/
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#define _PAGE_RW 0x0400 /* lsb PP bits, inverted in HW */
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#define _PAGE_USER 0x0800 /* msb PP bits */
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#define _PMD_PRESENT 0x0001
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#define _PMD_BAD 0x0ff0
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#define _PMD_PAGE_MASK 0x000c
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#define _PMD_PAGE_8M 0x000c
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#define _PTE_NONE_MASK _PAGE_ACCESSED
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/* Until my rework is finished, 8xx still needs atomic PTE updates */
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#define PTE_ATOMIC_UPDATES 1
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/* We need to add _PAGE_SHARED to kernel pages */
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#define _PAGE_KERNEL_RO (_PAGE_SHARED)
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PTE_8xx_H */
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