1d37374197
I don't really understand why gcc gives the error it does, but without
this patch, when building with CONFIG_HOTPLUG=n, I get errors like:
CC arch/x86_64/pci/../../i386/pci/fixup.o
arch/x86_64/pci/../../i386/pci/fixup.c: In function `pci_fixup_i450nx':
arch/x86_64/pci/../../i386/pci/fixup.c:13: error: pci_fixup_i450nx causes a section type conflict
The change is obviously correct: an array should be declared
__devinitdata rather that __devinit.
Signed-off-by: Roland Dreier <rolandd@cisco.com>
Acked-by: Martin J. Bligh <mbligh@mbligh.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
446 lines
15 KiB
C
446 lines
15 KiB
C
/*
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* Exceptions for specific devices. Usually work-arounds for fatal design flaws.
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*/
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#include <linux/delay.h>
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#include <linux/dmi.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include "pci.h"
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static void __devinit pci_fixup_i450nx(struct pci_dev *d)
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{
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/*
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* i450NX -- Find and scan all secondary buses on all PXB's.
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*/
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int pxb, reg;
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u8 busno, suba, subb;
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printk(KERN_WARNING "PCI: Searching for i450NX host bridges on %s\n", pci_name(d));
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reg = 0xd0;
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for(pxb=0; pxb<2; pxb++) {
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pci_read_config_byte(d, reg++, &busno);
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pci_read_config_byte(d, reg++, &suba);
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pci_read_config_byte(d, reg++, &subb);
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DBG("i450NX PXB %d: %02x/%02x/%02x\n", pxb, busno, suba, subb);
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if (busno)
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pci_scan_bus(busno, &pci_root_ops, NULL); /* Bus A */
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if (suba < subb)
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pci_scan_bus(suba+1, &pci_root_ops, NULL); /* Bus B */
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}
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pcibios_last_bus = -1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
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static void __devinit pci_fixup_i450gx(struct pci_dev *d)
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{
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/*
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* i450GX and i450KX -- Find and scan all secondary buses.
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* (called separately for each PCI bridge found)
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*/
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u8 busno;
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pci_read_config_byte(d, 0x4a, &busno);
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printk(KERN_INFO "PCI: i440KX/GX host bridge %s: secondary bus %02x\n", pci_name(d), busno);
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pci_scan_bus(busno, &pci_root_ops, NULL);
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pcibios_last_bus = -1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454GX, pci_fixup_i450gx);
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static void __devinit pci_fixup_umc_ide(struct pci_dev *d)
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{
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/*
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* UM8886BF IDE controller sets region type bits incorrectly,
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* therefore they look like memory despite of them being I/O.
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*/
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int i;
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printk(KERN_WARNING "PCI: Fixing base address flags for device %s\n", pci_name(d));
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for(i=0; i<4; i++)
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d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
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static void __devinit pci_fixup_ncr53c810(struct pci_dev *d)
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{
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/*
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* NCR 53C810 returns class code 0 (at least on some systems).
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* Fix class to be PCI_CLASS_STORAGE_SCSI
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*/
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if (!d->class) {
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printk(KERN_WARNING "PCI: fixing NCR 53C810 class code for %s\n", pci_name(d));
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d->class = PCI_CLASS_STORAGE_SCSI << 8;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, pci_fixup_ncr53c810);
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static void __devinit pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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DBG("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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static void __devinit pci_fixup_ide_trash(struct pci_dev *d)
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{
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int i;
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/*
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* Runs the fixup only for the first IDE controller
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* (Shai Fultheim - shai@ftcon.com)
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*/
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static int called = 0;
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if (called)
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return;
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called = 1;
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/*
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* There exist PCI IDE controllers which have utter garbage
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* in first four base registers. Ignore that.
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*/
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DBG("PCI: IDE base address trash cleared for %s\n", pci_name(d));
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for(i=0; i<4; i++)
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d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, pci_fixup_ide_trash);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_11, pci_fixup_ide_trash);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_9, pci_fixup_ide_trash);
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static void __devinit pci_fixup_latency(struct pci_dev *d)
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{
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/*
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* SiS 5597 and 5598 chipsets require latency timer set to
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* at most 32 to avoid lockups.
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*/
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DBG("PCI: Setting max latency to 32\n");
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pcibios_max_latency = 32;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
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static void __devinit pci_fixup_piix4_acpi(struct pci_dev *d)
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{
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/*
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* PIIX4 ACPI device: hardwired IRQ9
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*/
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d->irq = 9;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, pci_fixup_piix4_acpi);
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/*
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* Addresses issues with problems in the memory write queue timer in
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* certain VIA Northbridges. This bugfix is per VIA's specifications,
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* except for the KL133/KM133: clearing bit 5 on those Northbridges seems
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* to trigger a bug in its integrated ProSavage video card, which
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* causes screen corruption. We only clear bits 6 and 7 for that chipset,
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* until VIA can provide us with definitive information on why screen
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* corruption occurs, and what exactly those bits do.
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*
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* VIA 8363,8622,8361 Northbridges:
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* - bits 5, 6, 7 at offset 0x55 need to be turned off
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* VIA 8367 (KT266x) Northbridges:
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* - bits 5, 6, 7 at offset 0x95 need to be turned off
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* VIA 8363 rev 0x81/0x84 (KL133/KM133) Northbridges:
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* - bits 6, 7 at offset 0x55 need to be turned off
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*/
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#define VIA_8363_KL133_REVISION_ID 0x81
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#define VIA_8363_KM133_REVISION_ID 0x84
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static void __devinit pci_fixup_via_northbridge_bug(struct pci_dev *d)
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{
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u8 v;
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u8 revision;
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int where = 0x55;
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int mask = 0x1f; /* clear bits 5, 6, 7 by default */
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pci_read_config_byte(d, PCI_REVISION_ID, &revision);
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if (d->device == PCI_DEVICE_ID_VIA_8367_0) {
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/* fix pci bus latency issues resulted by NB bios error
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it appears on bug free^Wreduced kt266x's bios forces
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NB latency to zero */
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pci_write_config_byte(d, PCI_LATENCY_TIMER, 0);
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where = 0x95; /* the memory write queue timer register is
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different for the KT266x's: 0x95 not 0x55 */
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} else if (d->device == PCI_DEVICE_ID_VIA_8363_0 &&
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(revision == VIA_8363_KL133_REVISION_ID ||
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revision == VIA_8363_KM133_REVISION_ID)) {
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mask = 0x3f; /* clear only bits 6 and 7; clearing bit 5
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causes screen corruption on the KL133/KM133 */
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}
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pci_read_config_byte(d, where, &v);
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if (v & ~mask) {
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printk(KERN_WARNING "Disabling VIA memory write queue (PCI ID %04x, rev %02x): [%02x] %02x & %02x -> %02x\n", \
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d->device, revision, where, v, mask, v & mask);
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v &= mask;
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pci_write_config_byte(d, where, v);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, pci_fixup_via_northbridge_bug);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8622, pci_fixup_via_northbridge_bug);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, pci_fixup_via_northbridge_bug);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8367_0, pci_fixup_via_northbridge_bug);
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/*
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* For some reasons Intel decided that certain parts of their
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* 815, 845 and some other chipsets must look like PCI-to-PCI bridges
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* while they are obviously not. The 82801 family (AA, AB, BAM/CAM,
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* BA/CA/DB and E) PCI bridges are actually HUB-to-PCI ones, according
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* to Intel terminology. These devices do forward all addresses from
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* system to PCI bus no matter what are their window settings, so they are
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* "transparent" (or subtractive decoding) from programmers point of view.
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*/
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static void __devinit pci_fixup_transparent_bridge(struct pci_dev *dev)
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{
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if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
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(dev->device & 0xff00) == 0x2400)
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dev->transparent = 1;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixup_transparent_bridge);
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/*
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* Fixup for C1 Halt Disconnect problem on nForce2 systems.
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*
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* From information provided by "Allen Martin" <AMartin@nvidia.com>:
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*
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* A hang is caused when the CPU generates a very fast CONNECT/HALT cycle
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* sequence. Workaround is to set the SYSTEM_IDLE_TIMEOUT to 80 ns.
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* This allows the state-machine and timer to return to a proper state within
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* 80 ns of the CONNECT and probe appearing together. Since the CPU will not
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* issue another HALT within 80 ns of the initial HALT, the failure condition
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* is avoided.
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*/
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static void __init pci_fixup_nforce2(struct pci_dev *dev)
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{
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u32 val;
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/*
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* Chip Old value New value
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* C17 0x1F0FFF01 0x1F01FF01
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* C18D 0x9F0FFF01 0x9F01FF01
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*
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* Northbridge chip version may be determined by
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* reading the PCI revision ID (0xC1 or greater is C18D).
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*/
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pci_read_config_dword(dev, 0x6c, &val);
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/*
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* Apply fixup if needed, but don't touch disconnect state
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*/
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if ((val & 0x00FF0000) != 0x00010000) {
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printk(KERN_WARNING "PCI: nForce2 C1 Halt Disconnect fixup\n");
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pci_write_config_dword(dev, 0x6c, (val & 0xFF00FFFF) | 0x00010000);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2, pci_fixup_nforce2);
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/* Max PCI Express root ports */
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#define MAX_PCIEROOT 6
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static int quirk_aspm_offset[MAX_PCIEROOT << 3];
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#define GET_INDEX(a, b) ((((a) - PCI_DEVICE_ID_INTEL_MCH_PA) << 3) + ((b) & 7))
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static int quirk_pcie_aspm_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value)
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{
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return raw_pci_ops->read(0, bus->number, devfn, where, size, value);
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}
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/*
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* Replace the original pci bus ops for write with a new one that will filter
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* the request to insure ASPM cannot be enabled.
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*/
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static int quirk_pcie_aspm_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
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{
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u8 offset;
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offset = quirk_aspm_offset[GET_INDEX(bus->self->device, devfn)];
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if ((offset) && (where == offset))
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value = value & 0xfffffffc;
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return raw_pci_ops->write(0, bus->number, devfn, where, size, value);
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}
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static struct pci_ops quirk_pcie_aspm_ops = {
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.read = quirk_pcie_aspm_read,
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.write = quirk_pcie_aspm_write,
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};
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/*
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* Prevents PCI Express ASPM (Active State Power Management) being enabled.
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*
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* Save the register offset, where the ASPM control bits are located,
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* for each PCI Express device that is in the device list of
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* the root port in an array for fast indexing. Replace the bus ops
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* with the modified one.
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*/
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static void pcie_rootport_aspm_quirk(struct pci_dev *pdev)
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{
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int cap_base, i;
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struct pci_bus *pbus;
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struct pci_dev *dev;
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if ((pbus = pdev->subordinate) == NULL)
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return;
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/*
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* Check if the DID of pdev matches one of the six root ports. This
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* check is needed in the case this function is called directly by the
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* hot-plug driver.
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*/
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if ((pdev->device < PCI_DEVICE_ID_INTEL_MCH_PA) ||
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(pdev->device > PCI_DEVICE_ID_INTEL_MCH_PC1))
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return;
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if (list_empty(&pbus->devices)) {
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/*
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* If no device is attached to the root port at power-up or
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* after hot-remove, the pbus->devices is empty and this code
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* will set the offsets to zero and the bus ops to parent's bus
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* ops, which is unmodified.
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*/
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for (i= GET_INDEX(pdev->device, 0); i <= GET_INDEX(pdev->device, 7); ++i)
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quirk_aspm_offset[i] = 0;
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pbus->ops = pbus->parent->ops;
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} else {
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/*
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* If devices are attached to the root port at power-up or
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* after hot-add, the code loops through the device list of
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* each root port to save the register offsets and replace the
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* bus ops.
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*/
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list_for_each_entry(dev, &pbus->devices, bus_list) {
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/* There are 0 to 8 devices attached to this bus */
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cap_base = pci_find_capability(dev, PCI_CAP_ID_EXP);
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quirk_aspm_offset[GET_INDEX(pdev->device, dev->devfn)]= cap_base + 0x10;
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}
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pbus->ops = &quirk_pcie_aspm_ops;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA, pcie_rootport_aspm_quirk );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PA1, pcie_rootport_aspm_quirk );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB, pcie_rootport_aspm_quirk );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PB1, pcie_rootport_aspm_quirk );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC, pcie_rootport_aspm_quirk );
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_MCH_PC1, pcie_rootport_aspm_quirk );
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/*
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* Fixup to mark boot BIOS video selected by BIOS before it changes
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*
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* From information provided by "Jon Smirl" <jonsmirl@gmail.com>
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*
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* The standard boot ROM sequence for an x86 machine uses the BIOS
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* to select an initial video card for boot display. This boot video
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* card will have it's BIOS copied to C0000 in system RAM.
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* IORESOURCE_ROM_SHADOW is used to associate the boot video
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* card with this copy. On laptops this copy has to be used since
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* the main ROM may be compressed or combined with another image.
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* See pci_map_rom() for use of this flag. IORESOURCE_ROM_SHADOW
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* is marked here since the boot video device will be the only enabled
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* video device at this point.
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*/
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static void __devinit pci_fixup_video(struct pci_dev *pdev)
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{
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struct pci_dev *bridge;
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struct pci_bus *bus;
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u16 config;
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if ((pdev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
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return;
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/* Is VGA routed to us? */
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bus = pdev->bus;
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while (bus) {
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bridge = bus->self;
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if (bridge) {
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pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
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&config);
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if (!(config & PCI_BRIDGE_CTL_VGA))
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return;
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}
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bus = bus->parent;
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}
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pci_read_config_word(pdev, PCI_COMMAND, &config);
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if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
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pdev->resource[PCI_ROM_RESOURCE].flags |= IORESOURCE_ROM_SHADOW;
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printk(KERN_DEBUG "Boot video device is %s\n", pci_name(pdev));
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_video);
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/*
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* Some Toshiba laptops need extra code to enable their TI TSB43AB22/A.
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*
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* We pretend to bring them out of full D3 state, and restore the proper
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* IRQ, PCI cache line size, and BARs, otherwise the device won't function
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* properly. In some cases, the device will generate an interrupt on
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* the wrong IRQ line, causing any devices sharing the the line it's
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* *supposed* to use to be disabled by the kernel's IRQ debug code.
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*/
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static u16 toshiba_line_size;
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static struct dmi_system_id __devinitdata toshiba_ohci1394_dmi_table[] = {
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{
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.ident = "Toshiba PS5 based laptop",
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.matches = {
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DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
DMI_MATCH(DMI_PRODUCT_VERSION, "PS5"),
|
|
},
|
|
},
|
|
{
|
|
.ident = "Toshiba PSM4 based laptop",
|
|
.matches = {
|
|
DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
|
|
DMI_MATCH(DMI_PRODUCT_VERSION, "PSM4"),
|
|
},
|
|
},
|
|
{ }
|
|
};
|
|
|
|
static void __devinit pci_pre_fixup_toshiba_ohci1394(struct pci_dev *dev)
|
|
{
|
|
if (!dmi_check_system(toshiba_ohci1394_dmi_table))
|
|
return; /* only applies to certain Toshibas (so far) */
|
|
|
|
dev->current_state = PCI_D3cold;
|
|
pci_read_config_word(dev, PCI_CACHE_LINE_SIZE, &toshiba_line_size);
|
|
}
|
|
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0x8032,
|
|
pci_pre_fixup_toshiba_ohci1394);
|
|
|
|
static void __devinit pci_post_fixup_toshiba_ohci1394(struct pci_dev *dev)
|
|
{
|
|
if (!dmi_check_system(toshiba_ohci1394_dmi_table))
|
|
return; /* only applies to certain Toshibas (so far) */
|
|
|
|
/* Restore config space on Toshiba laptops */
|
|
mdelay(10);
|
|
pci_write_config_word(dev, PCI_CACHE_LINE_SIZE, toshiba_line_size);
|
|
pci_write_config_word(dev, PCI_INTERRUPT_LINE, dev->irq);
|
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
|
|
pci_resource_start(dev, 0));
|
|
pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
|
|
pci_resource_start(dev, 1));
|
|
}
|
|
DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_TI, 0x8032,
|
|
pci_post_fixup_toshiba_ohci1394);
|