1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
589 lines
15 KiB
C
589 lines
15 KiB
C
/*
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* Copyright (C) 2000 David J. Mckay (david.mckay@st.com)
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* This file contains the PCI routines required for the Galileo GT6411
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* PCI bridge as used on the Orion and Overdrive boards.
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <asm/overdrive/overdrive.h>
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#include <asm/overdrive/gt64111.h>
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/* After boot, we shift the Galileo registers so that they appear
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* in BANK6, along with IO space. This means we can have one contingous
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* lump of PCI address space without these registers appearing in the
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* middle of them
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*/
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#define GT64111_BASE_ADDRESS 0xbb000000
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#define GT64111_IO_BASE_ADDRESS 0x1000
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/* The GT64111 registers appear at this address to the SH4 after reset */
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#define RESET_GT64111_BASE_ADDRESS 0xb4000000
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/* Macros used to access the Galileo registers */
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#define RESET_GT64111_REG(x) (RESET_GT64111_BASE_ADDRESS+x)
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#define GT64111_REG(x) (GT64111_BASE_ADDRESS+x)
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#define RESET_GT_WRITE(x,v) writel((v),RESET_GT64111_REG(x))
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#define RESET_GT_READ(x) readl(RESET_GT64111_REG(x))
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#define GT_WRITE(x,v) writel((v),GT64111_REG(x))
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#define GT_WRITE_BYTE(x,v) writeb((v),GT64111_REG(x))
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#define GT_WRITE_SHORT(x,v) writew((v),GT64111_REG(x))
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#define GT_READ(x) readl(GT64111_REG(x))
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#define GT_READ_BYTE(x) readb(GT64111_REG(x))
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#define GT_READ_SHORT(x) readw(GT64111_REG(x))
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/* Where the various SH banks start at */
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#define SH_BANK4_ADR 0xb0000000
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#define SH_BANK5_ADR 0xb4000000
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#define SH_BANK6_ADR 0xb8000000
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/* Masks out everything but lines 28,27,26 */
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#define BANK_SELECT_MASK 0x1c000000
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#define SH4_TO_BANK(x) ( (x) & BANK_SELECT_MASK)
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/*
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* Masks used for address conversaion. Bank 6 is used for IO and
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* has all the address bits zeroed by the FPGA. Special case this
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*/
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#define MEMORY_BANK_MASK 0x1fffffff
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#define IO_BANK_MASK 0x03ffffff
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/* Mark bank 6 as the bank used for IO. You can change this in the FPGA code
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* if you want
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*/
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#define IO_BANK_ADR PCI_GTIO_BASE
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/* Will select the correct mask to apply depending on the SH$ address */
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#define SELECT_BANK_MASK(x) \
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( (SH4_TO_BANK(x)==SH4_TO_BANK(IO_BANK_ADR)) ? IO_BANK_MASK : MEMORY_BANK_MASK)
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/* Converts between PCI space and P2 region */
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#define SH4_TO_PCI(x) ((x)&SELECT_BANK_MASK(x))
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/* Various macros for figuring out what to stick in the Galileo registers.
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* You *really* don't want to figure this stuff out by hand, you always get
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* it wrong
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*/
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#define GT_MEM_LO_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7ff)
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#define GT_MEM_HI_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>21)&0x7f)
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#define GT_MEM_SUB_ADR(x) ((((unsigned)((x)&SELECT_BANK_MASK(x)))>>20)&0xff)
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#define PROGRAM_HI_LO(block,a,s) \
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GT_WRITE(block##_LO_DEC_ADR,GT_MEM_LO_ADR(a));\
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GT_WRITE(block##_HI_DEC_ADR,GT_MEM_HI_ADR(a+s-1))
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#define PROGRAM_SUB_HI_LO(block,a,s) \
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GT_WRITE(block##_LO_DEC_ADR,GT_MEM_SUB_ADR(a));\
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GT_WRITE(block##_HI_DEC_ADR,GT_MEM_SUB_ADR(a+s-1))
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/* We need to set the size, and the offset register */
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#define GT_BAR_MASK(x) ((x)&~0xfff)
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/* Macro to set up the BAR in the Galileo. Essentially used for the DRAM */
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#define PROGRAM_GT_BAR(block,a,s) \
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GT_WRITE(PCI_##block##_BANK_SIZE,GT_BAR_MASK((s-1)));\
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write_config_to_galileo(PCI_CONFIG_##block##_BASE_ADR,\
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GT_BAR_MASK(a))
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#define DISABLE_GT_BAR(block) \
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GT_WRITE(PCI_##block##_BANK_SIZE,0),\
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GT_CONFIG_WRITE(PCI_CONFIG_##block##_BASE_ADR,\
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0x80000000)
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/* Macros to disable things we are not going to use */
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#define DISABLE_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0x7ff);\
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GT_WRITE(x##_HI_DEC_ADR,0x00)
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#define DISABLE_SUB_DECODE(x) GT_WRITE(x##_LO_DEC_ADR,0xff);\
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GT_WRITE(x##_HI_DEC_ADR,0x00)
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static void __init reset_pci(void)
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{
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/* Set RESET_PCI bit high */
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writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
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udelay(250);
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/* Set RESET_PCI bit low */
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writeb(readb(OVERDRIVE_CTRL) & RESET_PCI_MASK, OVERDRIVE_CTRL);
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udelay(250);
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writeb(readb(OVERDRIVE_CTRL) | ENABLE_PCI_BIT, OVERDRIVE_CTRL);
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udelay(250);
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}
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static int write_config_to_galileo(int where, u32 val);
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#define GT_CONFIG_WRITE(where,val) write_config_to_galileo(where,val)
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#define ENABLE_PCI_DRAM
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#ifdef TEST_DRAM
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/* Test function to check out if the PCI DRAM is working OK */
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static int /* __init */ test_dram(unsigned *base, unsigned size)
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{
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unsigned *p = base;
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unsigned *end = (unsigned *) (((unsigned) base) + size);
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unsigned w;
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for (p = base; p < end; p++) {
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*p = 0xffffffff;
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if (*p != 0xffffffff) {
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printk("AAARGH -write failed!!! at %p is %x\n", p,
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*p);
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return 0;
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}
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*p = 0x0;
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if (*p != 0x0) {
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printk("AAARGH -write failed!!!\n");
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return 0;
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}
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}
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for (p = base; p < end; p++) {
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*p = (unsigned) p;
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if (*p != (unsigned) p) {
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printk("Failed at 0x%p, actually is 0x%x\n", p,
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*p);
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return 0;
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}
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}
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for (p = base; p < end; p++) {
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w = ((unsigned) p & 0xffff0000);
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*p = w | (w >> 16);
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}
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for (p = base; p < end; p++) {
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w = ((unsigned) p & 0xffff0000);
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w |= (w >> 16);
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if (*p != w) {
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printk
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("Failed at 0x%p, should be 0x%x actually is 0x%x\n",
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p, w, *p);
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return 0;
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}
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}
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return 1;
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}
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#endif
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/* Function to set up and initialise the galileo. This sets up the BARS,
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* maps the DRAM into the address space etc,etc
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*/
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int __init galileo_init(void)
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{
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reset_pci();
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/* Now shift the galileo regs into this block */
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RESET_GT_WRITE(INTERNAL_SPACE_DEC,
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GT_MEM_LO_ADR(GT64111_BASE_ADDRESS));
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/* Should have a sanity check here, that you can read back at the new
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* address what you just wrote
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*/
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/* Disable decode for all regions */
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DISABLE_DECODE(RAS10);
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DISABLE_DECODE(RAS32);
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DISABLE_DECODE(CS20);
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DISABLE_DECODE(CS3);
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DISABLE_DECODE(PCI_IO);
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DISABLE_DECODE(PCI_MEM0);
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DISABLE_DECODE(PCI_MEM1);
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/* Disable all BARS */
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GT_WRITE(BAR_ENABLE_ADR, 0x1ff);
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DISABLE_GT_BAR(RAS10);
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DISABLE_GT_BAR(RAS32);
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DISABLE_GT_BAR(CS20);
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DISABLE_GT_BAR(CS3);
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/* Tell the BAR where the IO registers now are */
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GT_CONFIG_WRITE(PCI_CONFIG_INT_REG_IO_ADR,GT_BAR_MASK(
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(GT64111_IO_BASE_ADDRESS &
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IO_BANK_MASK)));
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/* set up a 112 Mb decode */
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PROGRAM_HI_LO(PCI_MEM0, SH_BANK4_ADR, 112 * 1024 * 1024);
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/* Set up a 32 MB io space decode */
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PROGRAM_HI_LO(PCI_IO, IO_BANK_ADR, 32 * 1024 * 1024);
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#ifdef ENABLE_PCI_DRAM
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/* Program up the DRAM configuration - there is DRAM only in bank 0 */
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/* Now set up the DRAM decode */
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PROGRAM_HI_LO(RAS10, PCI_DRAM_BASE, PCI_DRAM_SIZE);
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/* And the sub decode */
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PROGRAM_SUB_HI_LO(RAS0, PCI_DRAM_BASE, PCI_DRAM_SIZE);
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DISABLE_SUB_DECODE(RAS1);
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/* Set refresh rate */
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GT_WRITE(DRAM_BANK0_PARMS, 0x3f);
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GT_WRITE(DRAM_CFG, 0x100);
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/* we have to lob off the top bits rememeber!! */
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PROGRAM_GT_BAR(RAS10, SH4_TO_PCI(PCI_DRAM_BASE), PCI_DRAM_SIZE);
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#endif
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/* We are only interested in decoding RAS10 and the Galileo's internal
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* registers (as IO) on the PCI bus
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*/
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#ifdef ENABLE_PCI_DRAM
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GT_WRITE(BAR_ENABLE_ADR, (~((1 << 8) | (1 << 3))) & 0x1ff);
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#else
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GT_WRITE(BAR_ENABLE_ADR, (~(1 << 3)) & 0x1ff);
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#endif
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/* Change the class code to host bridge, it actually powers up
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* as a memory controller
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*/
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GT_CONFIG_WRITE(8, 0x06000011);
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/* Allow the galileo to master the PCI bus */
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GT_CONFIG_WRITE(PCI_COMMAND,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
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PCI_COMMAND_IO);
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#if 0
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printk("Testing PCI DRAM - ");
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if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
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printk("Passed\n");
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}else {
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printk("FAILED\n");
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}
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#endif
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return 0;
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}
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#define SET_CONFIG_BITS(bus,devfn,where)\
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((1<<31) | ((bus) << 16) | ((devfn) << 8) | ((where) & ~3))
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#define CONFIG_CMD(dev, where) SET_CONFIG_BITS((dev)->bus->number,(dev)->devfn,where)
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/* This write to the galileo config registers, unlike the functions below, can
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* be used before the PCI subsystem has started up
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*/
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static int __init write_config_to_galileo(int where, u32 val)
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{
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GT_WRITE(PCI_CFG_ADR, SET_CONFIG_BITS(0, 0, where));
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GT_WRITE(PCI_CFG_DATA, val);
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return 0;
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}
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/* We exclude the galileo and slot 31, the galileo because I don't know how to stop
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* the setup code shagging up the setup I have done on it, and 31 because the whole
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* thing locks up if you try to access that slot (which doesn't exist of course anyway
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*/
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#define EXCLUDED_DEV(dev) ((dev->bus->number==0) && ((PCI_SLOT(dev->devfn)==0) || (PCI_SLOT(dev->devfn) == 31)))
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static int galileo_read_config_byte(struct pci_dev *dev, int where,
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u8 * val)
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{
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/* I suspect this doesn't work because this drives a special cycle ? */
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if (EXCLUDED_DEV(dev)) {
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*val = 0xff;
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return PCIBIOS_SUCCESSFUL;
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}
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/* Start the config cycle */
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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/* Read back the result */
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*val = GT_READ_BYTE(PCI_CFG_DATA + (where & 3));
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return PCIBIOS_SUCCESSFUL;
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}
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static int galileo_read_config_word(struct pci_dev *dev, int where,
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u16 * val)
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{
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if (EXCLUDED_DEV(dev)) {
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*val = 0xffff;
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return PCIBIOS_SUCCESSFUL;
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}
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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*val = GT_READ_SHORT(PCI_CFG_DATA + (where & 2));
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return PCIBIOS_SUCCESSFUL;
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}
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static int galileo_read_config_dword(struct pci_dev *dev, int where,
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u32 * val)
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{
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if (EXCLUDED_DEV(dev)) {
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*val = 0xffffffff;
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return PCIBIOS_SUCCESSFUL;
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}
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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*val = GT_READ(PCI_CFG_DATA);
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return PCIBIOS_SUCCESSFUL;
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}
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static int galileo_write_config_byte(struct pci_dev *dev, int where,
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u8 val)
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{
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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GT_WRITE_BYTE(PCI_CFG_DATA + (where & 3), val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int galileo_write_config_word(struct pci_dev *dev, int where,
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u16 val)
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{
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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GT_WRITE_SHORT(PCI_CFG_DATA + (where & 2), val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int galileo_write_config_dword(struct pci_dev *dev, int where,
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u32 val)
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{
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GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
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GT_WRITE(PCI_CFG_DATA, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_config_ops = {
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galileo_read_config_byte,
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galileo_read_config_word,
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galileo_read_config_dword,
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galileo_write_config_byte,
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galileo_write_config_word,
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galileo_write_config_dword
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};
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/* Everything hangs off this */
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static struct pci_bus *pci_root_bus;
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static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
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{
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return PCI_SLOT(dev->devfn);
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}
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static int __init map_od_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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/* Slot 1: Galileo
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* Slot 2: PCI Slot 1
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* Slot 3: PCI Slot 2
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* Slot 4: ESS
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*/
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switch (slot) {
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case 2:
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return OVERDRIVE_PCI_IRQ1;
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case 3:
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/* Note this assumes you have a hacked card in slot 2 */
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return OVERDRIVE_PCI_IRQ2;
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case 4:
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return OVERDRIVE_ESS_IRQ;
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default:
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/* printk("PCI: Unexpected IRQ mapping request for slot %d\n", slot); */
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return -1;
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}
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}
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void __init
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pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
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{
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ranges->io_start -= bus->resource[0]->start;
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ranges->io_end -= bus->resource[0]->start;
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ranges->mem_start -= bus->resource[1]->start;
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ranges->mem_end -= bus->resource[1]->start;
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}
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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printk("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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void __init pcibios_init(void)
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{
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static struct resource galio,galmem;
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/* Allocate the registers used by the Galileo */
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galio.flags = IORESOURCE_IO;
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galio.name = "Galileo GT64011";
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galmem.flags = IORESOURCE_MEM|IORESOURCE_PREFETCH;
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galmem.name = "Galileo GT64011 DRAM";
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allocate_resource(&ioport_resource, &galio, 256,
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GT64111_IO_BASE_ADDRESS,GT64111_IO_BASE_ADDRESS+256, 256, NULL, NULL);
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allocate_resource(&iomem_resource, &galmem,PCI_DRAM_SIZE,
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PHYSADDR(PCI_DRAM_BASE), PHYSADDR(PCI_DRAM_BASE)+PCI_DRAM_SIZE,
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PCI_DRAM_SIZE, NULL, NULL);
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/* ok, do the scan man */
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pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
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pci_assign_unassigned_resources();
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pci_fixup_irqs(no_swizzle, map_od_irq);
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#ifdef TEST_DRAM
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printk("Testing PCI DRAM - ");
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if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
|
|
printk("Passed\n");
|
|
}else {
|
|
printk("FAILED\n");
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
char * __init pcibios_setup(char *str)
|
|
{
|
|
return str;
|
|
}
|
|
|
|
|
|
|
|
int pcibios_enable_device(struct pci_dev *dev)
|
|
{
|
|
|
|
u16 cmd, old_cmd;
|
|
int idx;
|
|
struct resource *r;
|
|
|
|
pci_read_config_word(dev, PCI_COMMAND, &cmd);
|
|
old_cmd = cmd;
|
|
for (idx = 0; idx < 6; idx++) {
|
|
r = dev->resource + idx;
|
|
if (!r->start && r->end) {
|
|
printk(KERN_ERR
|
|
"PCI: Device %s not available because"
|
|
" of resource collisions\n",
|
|
pci_name(dev));
|
|
return -EINVAL;
|
|
}
|
|
if (r->flags & IORESOURCE_IO)
|
|
cmd |= PCI_COMMAND_IO;
|
|
if (r->flags & IORESOURCE_MEM)
|
|
cmd |= PCI_COMMAND_MEMORY;
|
|
}
|
|
if (cmd != old_cmd) {
|
|
printk("PCI: enabling device %s (%04x -> %04x)\n",
|
|
pci_name(dev), old_cmd, cmd);
|
|
pci_write_config_word(dev, PCI_COMMAND, cmd);
|
|
}
|
|
return 0;
|
|
|
|
}
|
|
|
|
/* We should do some optimisation work here I think. Ok for now though */
|
|
void __init pcibios_fixup_bus(struct pci_bus *bus)
|
|
{
|
|
|
|
}
|
|
|
|
void pcibios_align_resource(void *data, struct resource *res,
|
|
unsigned long size)
|
|
{
|
|
}
|
|
|
|
void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
|
|
struct resource *res, int resource)
|
|
{
|
|
|
|
unsigned long where, size;
|
|
u32 reg;
|
|
|
|
|
|
printk("PCI: Assigning %3s %08lx to %s\n",
|
|
res->flags & IORESOURCE_IO ? "IO" : "MEM",
|
|
res->start, dev->name);
|
|
|
|
where = PCI_BASE_ADDRESS_0 + resource * 4;
|
|
size = res->end - res->start;
|
|
|
|
pci_read_config_dword(dev, where, ®);
|
|
reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
|
|
pci_write_config_dword(dev, where, reg);
|
|
}
|
|
|
|
|
|
void __init pcibios_update_irq(struct pci_dev *dev, int irq)
|
|
{
|
|
printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
|
|
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
|
|
}
|
|
|
|
/*
|
|
* If we set up a device for bus mastering, we need to check the latency
|
|
* timer as certain crappy BIOSes forget to set it properly.
|
|
*/
|
|
unsigned int pcibios_max_latency = 255;
|
|
|
|
void pcibios_set_master(struct pci_dev *dev)
|
|
{
|
|
u8 lat;
|
|
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
|
|
if (lat < 16)
|
|
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
|
|
else if (lat > pcibios_max_latency)
|
|
lat = pcibios_max_latency;
|
|
else
|
|
return;
|
|
printk("PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
|
|
pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
|
|
}
|