1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
705 lines
16 KiB
C
705 lines
16 KiB
C
/* linux/drivers/mtd/nand/s3c2410.c
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*
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* Copyright (c) 2004 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* Samsung S3C2410 NAND driver
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*
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* Changelog:
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* 21-Sep-2004 BJD Initial version
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* 23-Sep-2004 BJD Mulitple device support
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* 28-Sep-2004 BJD Fixed ECC placement for Hardware mode
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* 12-Oct-2004 BJD Fixed errors in use of platform data
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*
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* $Id: s3c2410.c,v 1.7 2005/01/05 18:05:14 dwmw2 Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <config/mtd/nand/s3c2410/hwecc.h>
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#include <config/mtd/nand/s3c2410/debug.h>
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#ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
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#define DEBUG
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#endif
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/clock.h>
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#include <asm/arch/regs-nand.h>
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#include <asm/arch/nand.h>
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#define PFX "s3c2410-nand: "
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#ifdef CONFIG_MTD_NAND_S3C2410_HWECC
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static int hardware_ecc = 1;
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#else
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static int hardware_ecc = 0;
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#endif
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/* new oob placement block for use with hardware ecc generation
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*/
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static struct nand_oobinfo nand_hw_eccoob = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 3,
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.eccpos = {0, 1, 2 },
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.oobfree = { {8, 8} }
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};
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/* controller and mtd information */
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struct s3c2410_nand_info;
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struct s3c2410_nand_mtd {
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struct mtd_info mtd;
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struct nand_chip chip;
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struct s3c2410_nand_set *set;
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struct s3c2410_nand_info *info;
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int scan_res;
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};
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/* overview of the s3c2410 nand state */
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struct s3c2410_nand_info {
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/* mtd info */
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struct nand_hw_control controller;
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struct s3c2410_nand_mtd *mtds;
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struct s3c2410_platform_nand *platform;
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/* device info */
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struct device *device;
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struct resource *area;
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struct clk *clk;
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void *regs;
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int mtd_count;
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};
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/* conversion functions */
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static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
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{
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return container_of(mtd, struct s3c2410_nand_mtd, mtd);
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}
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static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
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{
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return s3c2410_nand_mtd_toours(mtd)->info;
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}
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static struct s3c2410_nand_info *to_nand_info(struct device *dev)
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{
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return dev_get_drvdata(dev);
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}
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static struct s3c2410_platform_nand *to_nand_plat(struct device *dev)
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{
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return dev->platform_data;
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}
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/* timing calculations */
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#define NS_IN_KHZ 10000000
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static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
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{
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int result;
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result = (wanted * NS_IN_KHZ) / clk;
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result++;
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pr_debug("result %d from %ld, %d\n", result, clk, wanted);
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if (result > max) {
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printk("%d ns is too big for current clock rate %ld\n",
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wanted, clk);
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return -1;
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}
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if (result < 1)
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result = 1;
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return result;
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}
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#define to_ns(ticks,clk) (((clk) * (ticks)) / NS_IN_KHZ)
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/* controller setup */
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static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
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struct device *dev)
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{
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struct s3c2410_platform_nand *plat = to_nand_plat(dev);
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unsigned int tacls, twrph0, twrph1;
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unsigned long clkrate = clk_get_rate(info->clk);
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unsigned long cfg;
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/* calculate the timing information for the controller */
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if (plat != NULL) {
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tacls = s3c2410_nand_calc_rate(plat->tacls, clkrate, 8);
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twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
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twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
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} else {
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/* default timings */
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tacls = 8;
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twrph0 = 8;
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twrph1 = 8;
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}
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if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
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printk(KERN_ERR PFX "cannot get timings suitable for board\n");
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return -EINVAL;
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}
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printk(KERN_INFO PFX "timing: Tacls %ldns, Twrph0 %ldns, Twrph1 %ldns\n",
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to_ns(tacls, clkrate),
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to_ns(twrph0, clkrate),
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to_ns(twrph1, clkrate));
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls-1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1);
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pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
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writel(cfg, info->regs + S3C2410_NFCONF);
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return 0;
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}
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/* select chip */
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static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
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{
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struct s3c2410_nand_info *info;
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struct s3c2410_nand_mtd *nmtd;
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struct nand_chip *this = mtd->priv;
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unsigned long cur;
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nmtd = this->priv;
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info = nmtd->info;
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cur = readl(info->regs + S3C2410_NFCONF);
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if (chip == -1) {
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cur |= S3C2410_NFCONF_nFCE;
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} else {
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if (chip > nmtd->set->nr_chips) {
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printk(KERN_ERR PFX "chip %d out of range\n", chip);
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return;
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}
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if (info->platform != NULL) {
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if (info->platform->select_chip != NULL)
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(info->platform->select_chip)(nmtd->set, chip);
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}
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cur &= ~S3C2410_NFCONF_nFCE;
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}
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writel(cur, info->regs + S3C2410_NFCONF);
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}
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/* command and control functions */
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static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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unsigned long cur;
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switch (cmd) {
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case NAND_CTL_SETNCE:
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cur = readl(info->regs + S3C2410_NFCONF);
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cur &= ~S3C2410_NFCONF_nFCE;
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writel(cur, info->regs + S3C2410_NFCONF);
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break;
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case NAND_CTL_CLRNCE:
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cur = readl(info->regs + S3C2410_NFCONF);
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cur |= S3C2410_NFCONF_nFCE;
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writel(cur, info->regs + S3C2410_NFCONF);
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break;
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/* we don't need to implement these */
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case NAND_CTL_SETCLE:
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case NAND_CTL_CLRCLE:
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case NAND_CTL_SETALE:
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case NAND_CTL_CLRALE:
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pr_debug(PFX "s3c2410_nand_hwcontrol(%d) unusedn", cmd);
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break;
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}
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}
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/* s3c2410_nand_command
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*
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* This function implements sending commands and the relevant address
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* information to the chip, via the hardware controller. Since the
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* S3C2410 generates the correct ALE/CLE signaling automatically, we
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* do not need to use hwcontrol.
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*/
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static void s3c2410_nand_command (struct mtd_info *mtd, unsigned command,
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int column, int page_addr)
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{
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register struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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register struct nand_chip *this = mtd->priv;
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->oobblock) {
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/* OOB area */
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column -= mtd->oobblock;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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writeb(readcmd, info->regs + S3C2410_NFCMD);
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}
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writeb(command, info->regs + S3C2410_NFCMD);
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/* Set ALE and clear CLE to start address cycle */
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if (column != -1 || page_addr != -1) {
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/* Serially input address */
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if (column != -1) {
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/* Adjust columns for 16 bit buswidth */
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if (this->options & NAND_BUSWIDTH_16)
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column >>= 1;
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writeb(column, info->regs + S3C2410_NFADDR);
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}
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if (page_addr != -1) {
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writeb((unsigned char) (page_addr), info->regs + S3C2410_NFADDR);
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writeb((unsigned char) (page_addr >> 8), info->regs + S3C2410_NFADDR);
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/* One more address cycle for higher density devices */
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if (this->chipsize & 0x0c000000)
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writeb((unsigned char) ((page_addr >> 16) & 0x0f),
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info->regs + S3C2410_NFADDR);
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}
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/* Latch in address */
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}
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/*
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* program and erase have their own busy handlers
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* status and sequential in needs no delay
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_SEQIN:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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if (this->dev_ready)
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break;
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udelay(this->chip_delay);
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writeb(NAND_CMD_STATUS, info->regs + S3C2410_NFCMD);
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while ( !(this->read_byte(mtd) & 0x40));
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return;
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/* This applies to read commands */
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default:
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/*
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* If we don't have access to the busy pin, we apply the given
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* command delay
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*/
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if (!this->dev_ready) {
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udelay (this->chip_delay);
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return;
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}
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}
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/* Apply this short delay always to ensure that we do wait tWB in
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* any case on any machine. */
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ndelay (100);
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/* wait until command is processed */
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while (!this->dev_ready(mtd));
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}
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/* s3c2410_nand_devready()
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*
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* returns 0 if the nand is busy, 1 if it is ready
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*/
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static int s3c2410_nand_devready(struct mtd_info *mtd)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
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}
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/* ECC handling functions */
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n",
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mtd, dat, read_ecc, calc_ecc);
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pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
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read_ecc[0], read_ecc[1], read_ecc[2],
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calc_ecc[0], calc_ecc[1], calc_ecc[2]);
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if (read_ecc[0] == calc_ecc[0] &&
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read_ecc[1] == calc_ecc[1] &&
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read_ecc[2] == calc_ecc[2])
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return 0;
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/* we curently have no method for correcting the error */
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return -1;
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}
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static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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unsigned long ctrl;
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ctrl = readl(info->regs + S3C2410_NFCONF);
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ctrl |= S3C2410_NFCONF_INITECC;
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writel(ctrl, info->regs + S3C2410_NFCONF);
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}
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static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
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ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
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ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
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ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
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pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
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ecc_code[0], ecc_code[1], ecc_code[2]);
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return 0;
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}
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/* over-ride the standard functions for a little more speed? */
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static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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readsb(this->IO_ADDR_R, buf, len);
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}
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static void s3c2410_nand_write_buf(struct mtd_info *mtd,
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const u_char *buf, int len)
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{
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struct nand_chip *this = mtd->priv;
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writesb(this->IO_ADDR_W, buf, len);
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}
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/* device management functions */
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static int s3c2410_nand_remove(struct device *dev)
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{
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struct s3c2410_nand_info *info = to_nand_info(dev);
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dev_set_drvdata(dev, NULL);
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if (info == NULL)
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return 0;
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/* first thing we need to do is release all our mtds
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* and their partitions, then go through freeing the
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* resources used
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*/
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if (info->mtds != NULL) {
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struct s3c2410_nand_mtd *ptr = info->mtds;
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int mtdno;
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for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
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pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
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nand_release(&ptr->mtd);
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}
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kfree(info->mtds);
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}
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/* free the common resources */
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if (info->clk != NULL && !IS_ERR(info->clk)) {
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clk_disable(info->clk);
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clk_unuse(info->clk);
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clk_put(info->clk);
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}
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if (info->regs != NULL) {
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iounmap(info->regs);
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info->regs = NULL;
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}
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if (info->area != NULL) {
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release_resource(info->area);
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kfree(info->area);
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info->area = NULL;
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}
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kfree(info);
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return 0;
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}
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#ifdef CONFIG_MTD_PARTITIONS
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static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
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struct s3c2410_nand_mtd *mtd,
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struct s3c2410_nand_set *set)
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{
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if (set == NULL)
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return add_mtd_device(&mtd->mtd);
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if (set->nr_partitions > 0 && set->partitions != NULL) {
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return add_mtd_partitions(&mtd->mtd,
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set->partitions,
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set->nr_partitions);
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}
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return add_mtd_device(&mtd->mtd);
|
|
}
|
|
#else
|
|
static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *mtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
return add_mtd_device(&mtd->mtd);
|
|
}
|
|
#endif
|
|
|
|
/* s3c2410_nand_init_chip
|
|
*
|
|
* init a single instance of an chip
|
|
*/
|
|
|
|
static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
|
|
struct s3c2410_nand_mtd *nmtd,
|
|
struct s3c2410_nand_set *set)
|
|
{
|
|
struct nand_chip *chip = &nmtd->chip;
|
|
|
|
chip->IO_ADDR_R = (char *)info->regs + S3C2410_NFDATA;
|
|
chip->IO_ADDR_W = (char *)info->regs + S3C2410_NFDATA;
|
|
chip->hwcontrol = s3c2410_nand_hwcontrol;
|
|
chip->dev_ready = s3c2410_nand_devready;
|
|
chip->cmdfunc = s3c2410_nand_command;
|
|
chip->write_buf = s3c2410_nand_write_buf;
|
|
chip->read_buf = s3c2410_nand_read_buf;
|
|
chip->select_chip = s3c2410_nand_select_chip;
|
|
chip->chip_delay = 50;
|
|
chip->priv = nmtd;
|
|
chip->options = 0;
|
|
chip->controller = &info->controller;
|
|
|
|
nmtd->info = info;
|
|
nmtd->mtd.priv = chip;
|
|
nmtd->set = set;
|
|
|
|
if (hardware_ecc) {
|
|
chip->correct_data = s3c2410_nand_correct_data;
|
|
chip->enable_hwecc = s3c2410_nand_enable_hwecc;
|
|
chip->calculate_ecc = s3c2410_nand_calculate_ecc;
|
|
chip->eccmode = NAND_ECC_HW3_512;
|
|
chip->autooob = &nand_hw_eccoob;
|
|
} else {
|
|
chip->eccmode = NAND_ECC_SOFT;
|
|
}
|
|
}
|
|
|
|
/* s3c2410_nand_probe
|
|
*
|
|
* called by device layer when it finds a device matching
|
|
* one our driver can handled. This code checks to see if
|
|
* it can allocate all necessary resources then calls the
|
|
* nand layer to look for devices
|
|
*/
|
|
|
|
static int s3c2410_nand_probe(struct device *dev)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(dev);
|
|
struct s3c2410_platform_nand *plat = to_nand_plat(dev);
|
|
struct s3c2410_nand_info *info;
|
|
struct s3c2410_nand_mtd *nmtd;
|
|
struct s3c2410_nand_set *sets;
|
|
struct resource *res;
|
|
int err = 0;
|
|
int size;
|
|
int nr_sets;
|
|
int setno;
|
|
|
|
pr_debug("s3c2410_nand_probe(%p)\n", dev);
|
|
|
|
info = kmalloc(sizeof(*info), GFP_KERNEL);
|
|
if (info == NULL) {
|
|
printk(KERN_ERR PFX "no memory for flash info\n");
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
memzero(info, sizeof(*info));
|
|
dev_set_drvdata(dev, info);
|
|
|
|
spin_lock_init(&info->controller.lock);
|
|
|
|
/* get the clock source and enable it */
|
|
|
|
info->clk = clk_get(dev, "nand");
|
|
if (IS_ERR(info->clk)) {
|
|
printk(KERN_ERR PFX "failed to get clock");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
clk_use(info->clk);
|
|
clk_enable(info->clk);
|
|
|
|
/* allocate and map the resource */
|
|
|
|
res = pdev->resource; /* assume that the flash has one resource */
|
|
size = res->end - res->start + 1;
|
|
|
|
info->area = request_mem_region(res->start, size, pdev->name);
|
|
|
|
if (info->area == NULL) {
|
|
printk(KERN_ERR PFX "cannot reserve register region\n");
|
|
err = -ENOENT;
|
|
goto exit_error;
|
|
}
|
|
|
|
info->device = dev;
|
|
info->platform = plat;
|
|
info->regs = ioremap(res->start, size);
|
|
|
|
if (info->regs == NULL) {
|
|
printk(KERN_ERR PFX "cannot reserve register region\n");
|
|
err = -EIO;
|
|
goto exit_error;
|
|
}
|
|
|
|
printk(KERN_INFO PFX "mapped registers at %p\n", info->regs);
|
|
|
|
/* initialise the hardware */
|
|
|
|
err = s3c2410_nand_inithw(info, dev);
|
|
if (err != 0)
|
|
goto exit_error;
|
|
|
|
sets = (plat != NULL) ? plat->sets : NULL;
|
|
nr_sets = (plat != NULL) ? plat->nr_sets : 1;
|
|
|
|
info->mtd_count = nr_sets;
|
|
|
|
/* allocate our information */
|
|
|
|
size = nr_sets * sizeof(*info->mtds);
|
|
info->mtds = kmalloc(size, GFP_KERNEL);
|
|
if (info->mtds == NULL) {
|
|
printk(KERN_ERR PFX "failed to allocate mtd storage\n");
|
|
err = -ENOMEM;
|
|
goto exit_error;
|
|
}
|
|
|
|
memzero(info->mtds, size);
|
|
|
|
/* initialise all possible chips */
|
|
|
|
nmtd = info->mtds;
|
|
|
|
for (setno = 0; setno < nr_sets; setno++, nmtd++) {
|
|
pr_debug("initialising set %d (%p, info %p)\n",
|
|
setno, nmtd, info);
|
|
|
|
s3c2410_nand_init_chip(info, nmtd, sets);
|
|
|
|
nmtd->scan_res = nand_scan(&nmtd->mtd,
|
|
(sets) ? sets->nr_chips : 1);
|
|
|
|
if (nmtd->scan_res == 0) {
|
|
s3c2410_nand_add_partition(info, nmtd, sets);
|
|
}
|
|
|
|
if (sets != NULL)
|
|
sets++;
|
|
}
|
|
|
|
pr_debug("initialised ok\n");
|
|
return 0;
|
|
|
|
exit_error:
|
|
s3c2410_nand_remove(dev);
|
|
|
|
if (err == 0)
|
|
err = -EINVAL;
|
|
return err;
|
|
}
|
|
|
|
static struct device_driver s3c2410_nand_driver = {
|
|
.name = "s3c2410-nand",
|
|
.bus = &platform_bus_type,
|
|
.probe = s3c2410_nand_probe,
|
|
.remove = s3c2410_nand_remove,
|
|
};
|
|
|
|
static int __init s3c2410_nand_init(void)
|
|
{
|
|
printk("S3C2410 NAND Driver, (c) 2004 Simtec Electronics\n");
|
|
return driver_register(&s3c2410_nand_driver);
|
|
}
|
|
|
|
static void __exit s3c2410_nand_exit(void)
|
|
{
|
|
driver_unregister(&s3c2410_nand_driver);
|
|
}
|
|
|
|
module_init(s3c2410_nand_init);
|
|
module_exit(s3c2410_nand_exit);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
|
|
MODULE_DESCRIPTION("S3C2410 MTD NAND driver");
|