14c89e7fc8
On ppc64, we independently define VMALLOCBASE and VMALLOC_START to be the same thing: the start of the vmalloc() area at 0xd000000000000000. VMALLOC_START is used much more widely, including in generic code, so this patch gets rid of the extraneous VMALLOCBASE. This does require moving the definitions of region IDs from page_64.h to pgtable.h, but they don't clearly belong in the former rather than the latter, anyway. While we're moving them, clean up the definitions of the REGION_IDs: - Abolish REGION_SIZE, it was only used once, to define REGION_MASK anyway - Define the specific region ids in terms of the REGION_ID() macro. - Define KERNEL_REGION_ID in terms of PAGE_OFFSET rather than KERNELBASE. It amounts to the same thing, but conceptually this is about the region of the linear mapping (which starts at PAGE_OFFSET) rather than of the kernel text itself (which is at KERNELBASE). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
231 lines
6.5 KiB
C
231 lines
6.5 KiB
C
/*
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* PowerPC64 SLB support.
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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* Based on earlier code writteh by:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/config.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/paca.h>
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#include <asm/cputable.h>
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#include <asm/cacheflush.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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extern void slb_allocate_realmode(unsigned long ea);
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extern void slb_allocate_user(unsigned long ea);
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static void slb_allocate(unsigned long ea)
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{
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/* Currently, we do real mode for all SLBs including user, but
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* that will change if we bring back dynamic VSIDs
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*/
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slb_allocate_realmode(ea);
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}
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static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
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{
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return (ea & ESID_MASK) | SLB_ESID_V | slot;
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}
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static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
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{
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return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | flags;
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}
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static inline void create_slbe(unsigned long ea, unsigned long flags,
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unsigned long entry)
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{
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asm volatile("slbmte %0,%1" :
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: "r" (mk_vsid_data(ea, flags)),
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"r" (mk_esid_data(ea, entry))
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: "memory" );
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}
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static void slb_flush_and_rebolt(void)
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{
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/* If you change this make sure you change SLB_NUM_BOLTED
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* appropriately too. */
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unsigned long linear_llp, virtual_llp, lflags, vflags;
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unsigned long ksp_esid_data;
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WARN_ON(!irqs_disabled());
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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virtual_llp = mmu_psize_defs[mmu_virtual_psize].sllp;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | virtual_llp;
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ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
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if ((ksp_esid_data & ESID_MASK) == PAGE_OFFSET)
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ksp_esid_data &= ~SLB_ESID_V;
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/* We need to do this all in asm, so we're sure we don't touch
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* the stack between the slbia and rebolting it. */
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asm volatile("isync\n"
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"slbia\n"
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/* Slot 1 - first VMALLOC segment */
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"slbmte %0,%1\n"
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/* Slot 2 - kernel stack */
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"slbmte %2,%3\n"
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"isync"
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:: "r"(mk_vsid_data(VMALLOC_START, vflags)),
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"r"(mk_esid_data(VMALLOC_START, 1)),
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"r"(mk_vsid_data(ksp_esid_data, lflags)),
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"r"(ksp_esid_data)
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: "memory");
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}
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/* Flush all user entries from the segment table of the current processor. */
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void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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{
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unsigned long offset = get_paca()->slb_cache_ptr;
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unsigned long esid_data = 0;
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unsigned long pc = KSTK_EIP(tsk);
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unsigned long stack = KSTK_ESP(tsk);
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unsigned long unmapped_base;
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if (offset <= SLB_CACHE_ENTRIES) {
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int i;
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asm volatile("isync" : : : "memory");
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for (i = 0; i < offset; i++) {
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esid_data = ((unsigned long)get_paca()->slb_cache[i]
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<< SID_SHIFT) | SLBIE_C;
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asm volatile("slbie %0" : : "r" (esid_data));
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}
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asm volatile("isync" : : : "memory");
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} else {
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slb_flush_and_rebolt();
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}
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/* Workaround POWER5 < DD2.1 issue */
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if (offset == 1 || offset > SLB_CACHE_ENTRIES)
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asm volatile("slbie %0" : : "r" (esid_data));
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get_paca()->slb_cache_ptr = 0;
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get_paca()->context = mm->context;
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#ifdef CONFIG_PPC_64K_PAGES
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get_paca()->pgdir = mm->pgd;
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#endif /* CONFIG_PPC_64K_PAGES */
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/*
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* preload some userspace segments into the SLB.
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*/
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if (test_tsk_thread_flag(tsk, TIF_32BIT))
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unmapped_base = TASK_UNMAPPED_BASE_USER32;
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else
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unmapped_base = TASK_UNMAPPED_BASE_USER64;
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if (is_kernel_addr(pc))
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return;
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slb_allocate(pc);
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if (GET_ESID(pc) == GET_ESID(stack))
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return;
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if (is_kernel_addr(stack))
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return;
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slb_allocate(stack);
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if ((GET_ESID(pc) == GET_ESID(unmapped_base))
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|| (GET_ESID(stack) == GET_ESID(unmapped_base)))
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return;
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if (is_kernel_addr(unmapped_base))
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return;
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slb_allocate(unmapped_base);
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}
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static inline void patch_slb_encoding(unsigned int *insn_addr,
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unsigned int immed)
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{
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/* Assume the instruction had a "0" immediate value, just
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* "or" in the new value
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*/
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*insn_addr |= immed;
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flush_icache_range((unsigned long)insn_addr, 4+
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(unsigned long)insn_addr);
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}
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void slb_initialize(void)
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{
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unsigned long linear_llp, virtual_llp;
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static int slb_encoding_inited;
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extern unsigned int *slb_miss_kernel_load_linear;
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extern unsigned int *slb_miss_kernel_load_virtual;
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extern unsigned int *slb_miss_user_load_normal;
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#ifdef CONFIG_HUGETLB_PAGE
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extern unsigned int *slb_miss_user_load_huge;
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unsigned long huge_llp;
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huge_llp = mmu_psize_defs[mmu_huge_psize].sllp;
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#endif
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/* Prepare our SLB miss handler based on our page size */
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linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
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virtual_llp = mmu_psize_defs[mmu_virtual_psize].sllp;
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if (!slb_encoding_inited) {
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slb_encoding_inited = 1;
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patch_slb_encoding(slb_miss_kernel_load_linear,
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SLB_VSID_KERNEL | linear_llp);
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patch_slb_encoding(slb_miss_kernel_load_virtual,
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SLB_VSID_KERNEL | virtual_llp);
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patch_slb_encoding(slb_miss_user_load_normal,
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SLB_VSID_USER | virtual_llp);
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DBG("SLB: linear LLP = %04x\n", linear_llp);
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DBG("SLB: virtual LLP = %04x\n", virtual_llp);
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#ifdef CONFIG_HUGETLB_PAGE
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patch_slb_encoding(slb_miss_user_load_huge,
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SLB_VSID_USER | huge_llp);
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DBG("SLB: huge LLP = %04x\n", huge_llp);
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#endif
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}
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/* On iSeries the bolted entries have already been set up by
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* the hypervisor from the lparMap data in head.S */
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#ifndef CONFIG_PPC_ISERIES
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{
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unsigned long lflags, vflags;
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lflags = SLB_VSID_KERNEL | linear_llp;
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vflags = SLB_VSID_KERNEL | virtual_llp;
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/* Invalidate the entire SLB (even slot 0) & all the ERATS */
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asm volatile("isync":::"memory");
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asm volatile("slbmte %0,%0"::"r" (0) : "memory");
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asm volatile("isync; slbia; isync":::"memory");
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create_slbe(PAGE_OFFSET, lflags, 0);
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/* VMALLOC space has 4K pages always for now */
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create_slbe(VMALLOC_START, vflags, 1);
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/* We don't bolt the stack for the time being - we're in boot,
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* so the stack is in the bolted segment. By the time it goes
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* elsewhere, we'll call _switch() which will bolt in the new
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* one. */
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asm volatile("isync":::"memory");
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}
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#endif /* CONFIG_PPC_ISERIES */
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get_paca()->stab_rr = SLB_NUM_BOLTED;
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}
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