74f6ae84b2
Add ddc/i2c support for i810fb. This will allow the driver to get display information, especially for monitors with fickle timings. The i2c support depends on CONFIG_FB_I810_GTF. Changed __init* to __devinit* Signed-off-by: Antonino Daplas <adaplas@pol.net> Signed-off-by: Alexander Nyberg <alexn@telia.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
298 lines
9.3 KiB
C
298 lines
9.3 KiB
C
/*-*- linux-c -*-
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* linux/drivers/video/i810.h -- Intel 810 General Definitions/Declarations
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*
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* Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
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* All Rights Reserved
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*
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive for
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* more details.
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*/
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#ifndef __I810_H__
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#define __I810_H__
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#include <linux/list.h>
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#include <linux/agp_backend.h>
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#include <linux/fb.h>
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#include <linux/i2c.h>
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#include <linux/i2c-id.h>
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#include <linux/i2c-algo-bit.h>
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#include <video/vga.h>
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/* Fence */
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#define TILEWALK_X (0 << 12)
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#define TILEWALK_Y (1 << 12)
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/* Raster ops */
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#define COLOR_COPY_ROP 0xF0
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#define PAT_COPY_ROP 0xCC
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#define CLEAR_ROP 0x00
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#define WHITE_ROP 0xFF
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#define INVERT_ROP 0x55
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#define XOR_ROP 0x5A
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/* 2D Engine definitions */
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#define SOLIDPATTERN 0x80000000
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#define NONSOLID 0x00000000
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#define BPP8 (0 << 24)
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#define BPP16 (1 << 24)
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#define BPP24 (2 << 24)
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#define PIXCONF8 (2 << 16)
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#define PIXCONF15 (4 << 16)
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#define PIXCONF16 (5 << 16)
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#define PIXCONF24 (6 << 16)
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#define PIXCONF32 (7 << 16)
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#define DYN_COLOR_EN (1 << 26)
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#define DYN_COLOR_DIS (0 << 26)
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#define INCREMENT 0x00000000
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#define DECREMENT (0x01 << 30)
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#define ARB_ON 0x00000001
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#define ARB_OFF 0x00000000
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#define SYNC_FLIP 0x00000000
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#define ASYNC_FLIP 0x00000040
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#define OPTYPE_MASK 0xE0000000
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#define PARSER_MASK 0x001F8000
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#define D2_MASK 0x001FC000 /* 2D mask */
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/* Instruction type */
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/* There are more but pertains to 3D */
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#define PARSER 0x00000000
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#define BLIT (0x02 << 29)
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#define RENDER (0x03 << 29)
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/* Parser */
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#define NOP 0x00 /* No operation, padding */
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#define BP_INT (0x01 << 23) /* Breakpoint interrupt */
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#define USR_INT (0x02 << 23) /* User interrupt */
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#define WAIT_FOR_EVNT (0x03 << 23) /* Wait for event */
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#define FLUSH (0x04 << 23)
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#define CONTEXT_SEL (0x05 << 23)
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#define REPORT_HEAD (0x07 << 23)
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#define ARB_ON_OFF (0x08 << 23)
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#define OVERLAY_FLIP (0x11 << 23)
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#define LOAD_SCAN_INC (0x12 << 23)
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#define LOAD_SCAN_EX (0x13 << 23)
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#define FRONT_BUFFER (0x14 << 23)
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#define DEST_BUFFER (0x15 << 23)
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#define Z_BUFFER (0x16 << 23)
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#define STORE_DWORD_IMM (0x20 << 23)
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#define STORE_DWORD_IDX (0x21 << 23)
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#define BATCH_BUFFER (0x30 << 23)
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/* Blit */
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#define SETUP_BLIT 0x00
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#define SETUP_MONO_PATTERN_SL_BLT (0x10 << 22)
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#define PIXEL_BLT (0x20 << 22)
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#define SCANLINE_BLT (0x21 << 22)
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#define TEXT_BLT (0x22 << 22)
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#define TEXT_IMM_BLT (0x30 << 22)
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#define COLOR_BLT (0x40 << 22)
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#define MONO_PAT_BLIT (0x42 << 22)
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#define SOURCE_COPY_BLIT (0x43 << 22)
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#define MONO_SOURCE_COPY_BLIT (0x44 << 22)
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#define SOURCE_COPY_IMMEDIATE (0x60 << 22)
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#define MONO_SOURCE_COPY_IMMEDIATE (0x61 << 22)
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#define VERSION_MAJOR 0
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#define VERSION_MINOR 9
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#define VERSION_TEENIE 0
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#define BRANCH_VERSION ""
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/* mvo: intel i815 */
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#ifndef PCI_DEVICE_ID_INTEL_82815_100
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#define PCI_DEVICE_ID_INTEL_82815_100 0x1102
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#endif
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#ifndef PCI_DEVICE_ID_INTEL_82815_NOAGP
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#define PCI_DEVICE_ID_INTEL_82815_NOAGP 0x1112
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#endif
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#ifndef PCI_DEVICE_ID_INTEL_82815_FULL_CTRL
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#define PCI_DEVICE_ID_INTEL_82815_FULL_CTRL 0x1130
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#endif
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/* General Defines */
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#define I810_PAGESIZE 4096
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#define MAX_DMA_SIZE (1024 * 4096)
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#define SAREA_SIZE 4096
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#define PCI_I810_MISCC 0x72
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#define MMIO_SIZE (512*1024)
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#define GTT_SIZE (16*1024)
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#define RINGBUFFER_SIZE (64*1024)
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#define CURSOR_SIZE 4096
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#define OFF 0
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#define ON 1
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#define MAX_KEY 256
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#define WAIT_COUNT 10000000
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#define IRING_PAD 8
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#define FONTDATAMAX 8192
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/* Masks (AND ops) and OR's */
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#define FB_START_MASK (0x3f << (32 - 6))
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#define MMIO_ADDR_MASK (0x1FFF << (32 - 13))
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#define FREQ_MASK 0x1EF
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#define SCR_OFF 0x20
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#define DRAM_ON 0x08
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#define DRAM_OFF 0xE7
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#define PG_ENABLE_MASK 0x01
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#define RING_SIZE_MASK (RINGBUFFER_SIZE - 1);
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/* defines for restoring registers partially */
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#define ADDR_MAP_MASK (0x07 << 5)
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#define DISP_CTRL ~0
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#define PIXCONF_0 (0x64 << 8)
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#define PIXCONF_2 (0xF3 << 24)
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#define PIXCONF_1 (0xF0 << 16)
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#define MN_MASK 0x3FF03FF
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#define P_OR (0x7 << 4)
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#define DAC_BIT (1 << 16)
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#define INTERLACE_BIT (1 << 7)
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#define IER_MASK (3 << 13)
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#define IMR_MASK (3 << 13)
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/* Power Management */
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#define DPMS_MASK 0xF0000
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#define POWERON 0x00000
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#define STANDBY 0x20000
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#define SUSPEND 0x80000
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#define POWERDOWN 0xA0000
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#define EMR_MASK ~0x3F
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#define FW_BLC_MASK ~(0x3F|(7 << 8)|(0x3F << 12)|(7 << 20))
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/* Ringbuffer */
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#define RBUFFER_START_MASK 0xFFFFF000
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#define RBUFFER_SIZE_MASK 0x001FF000
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#define RBUFFER_HEAD_MASK 0x001FFFFC
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#define RBUFFER_TAIL_MASK 0x001FFFF8
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/* Video Timings */
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#define REF_FREQ 24000000
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#define TARGET_N_MAX 30
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#define MAX_PIXELCLOCK 230000000
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#define MIN_PIXELCLOCK 15000000
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#define VFMAX 60
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#define VFMIN 60
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#define HFMAX 30000
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#define HFMIN 29000
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/* Cursor */
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#define CURSOR_ENABLE_MASK 0x1000
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#define CURSOR_MODE_64_TRANS 4
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#define CURSOR_MODE_64_XOR 5
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#define CURSOR_MODE_64_3C 6
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#define COORD_INACTIVE 0
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#define COORD_ACTIVE (1 << 4)
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#define EXTENDED_PALETTE 1
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/* AGP Memory Types*/
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#define AGP_NORMAL_MEMORY 0
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#define AGP_DCACHE_MEMORY 1
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#define AGP_PHYSICAL_MEMORY 2
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/* Allocated resource Flags */
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#define FRAMEBUFFER_REQ 1
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#define MMIO_REQ 2
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#define PCI_DEVICE_ENABLED 4
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#define HAS_FONTCACHE 8
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/* driver flags */
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#define HAS_MTRR 1
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#define HAS_ACCELERATION 2
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#define ALWAYS_SYNC 4
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#define LOCKUP 8
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struct gtt_data {
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struct agp_memory *i810_fb_memory;
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struct agp_memory *i810_cursor_memory;
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};
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struct mode_registers {
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u32 pixclock, M, N, P;
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u8 cr00, cr01, cr02, cr03;
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u8 cr04, cr05, cr06, cr07;
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u8 cr09, cr10, cr11, cr12;
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u8 cr13, cr15, cr16, cr30;
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u8 cr31, cr32, cr33, cr35, cr39;
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u32 bpp8_100, bpp16_100;
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u32 bpp24_100, bpp8_133;
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u32 bpp16_133, bpp24_133;
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u8 msr;
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};
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struct heap_data {
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unsigned long physical;
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__u8 __iomem *virtual;
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u32 offset;
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u32 size;
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};
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struct state_registers {
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u32 dclk_1d, dclk_2d, dclk_0ds;
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u32 pixconf, fw_blc, pgtbl_ctl;
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u32 fence0, hws_pga, dplystas;
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u16 bltcntl, hwstam, ier, iir, imr;
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u8 cr00, cr01, cr02, cr03, cr04;
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u8 cr05, cr06, cr07, cr08, cr09;
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u8 cr10, cr11, cr12, cr13, cr14;
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u8 cr15, cr16, cr17, cr80, gr10;
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u8 cr30, cr31, cr32, cr33, cr35;
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u8 cr39, cr41, cr70, sr01, msr;
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};
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struct i810fb_par;
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struct i810fb_i2c_chan {
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struct i810fb_par *par;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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};
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struct i810fb_par {
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struct mode_registers regs;
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struct state_registers hw_state;
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struct gtt_data i810_gtt;
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struct fb_ops i810fb_ops;
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struct pci_dev *dev;
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struct heap_data aperture;
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struct heap_data fb;
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struct heap_data iring;
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struct heap_data cursor_heap;
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struct vgastate state;
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struct i810fb_i2c_chan chan[2];
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atomic_t use_count;
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u32 pseudo_palette[17];
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unsigned long mmio_start_phys;
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u8 __iomem *mmio_start_virtual;
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u8 *edid;
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u32 pitch;
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u32 pixconf;
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u32 watermark;
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u32 mem_freq;
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u32 res_flags;
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u32 dev_flags;
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u32 cur_tail;
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u32 depth;
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u32 blit_bpp;
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u32 ovract;
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u32 cur_state;
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int mtrr_reg;
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u16 bltcntl;
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u8 interlace;
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};
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/*
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* Register I/O
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*/
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#define i810_readb(where, mmio) readb(mmio + where)
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#define i810_readw(where, mmio) readw(mmio + where)
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#define i810_readl(where, mmio) readl(mmio + where)
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#define i810_writeb(where, mmio, val) writeb(val, mmio + where)
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#define i810_writew(where, mmio, val) writew(val, mmio + where)
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#define i810_writel(where, mmio, val) writel(val, mmio + where)
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#endif /* __I810_H__ */
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