618 lines
16 KiB
C
618 lines
16 KiB
C
/*
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* This code largely moved from arch/i386/kernel/time.c.
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* See comments there for proper credits.
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*
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* 2004-06-25 Jesper Juhl
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* moved mark_offset_tsc below cpufreq_delayed_get to avoid gcc 3.4
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* failing to inline.
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*/
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/errno.h>
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#include <linux/cpufreq.h>
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#include <linux/string.h>
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#include <linux/jiffies.h>
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#include <asm/timer.h>
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#include <asm/io.h>
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/* processor.h for distable_tsc flag */
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#include <asm/processor.h>
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#include "io_ports.h"
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#include "mach_timer.h"
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#include <asm/hpet.h>
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#include <asm/i8253.h>
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#ifdef CONFIG_HPET_TIMER
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static unsigned long hpet_usec_quotient;
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static unsigned long hpet_last;
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static struct timer_opts timer_tsc;
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#endif
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static inline void cpufreq_delayed_get(void);
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int tsc_disable __devinitdata = 0;
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static int use_tsc;
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/* Number of usecs that the last interrupt was delayed */
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static int delay_at_last_interrupt;
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static unsigned long last_tsc_low; /* lsb 32 bits of Time Stamp Counter */
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static unsigned long last_tsc_high; /* msb 32 bits of Time Stamp Counter */
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static unsigned long long monotonic_base;
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static seqlock_t monotonic_lock = SEQLOCK_UNLOCKED;
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/* Avoid compensating for lost ticks before TSCs are synched */
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static int detect_lost_ticks;
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static int __init start_lost_tick_compensation(void)
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{
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detect_lost_ticks = 1;
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return 0;
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}
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late_initcall(start_lost_tick_compensation);
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/* convert from cycles(64bits) => nanoseconds (64bits)
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* basic equation:
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* ns = cycles / (freq / ns_per_sec)
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* ns = cycles * (ns_per_sec / freq)
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* ns = cycles * (10^9 / (cpu_khz * 10^3))
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* ns = cycles * (10^6 / cpu_khz)
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*
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* Then we use scaling math (suggested by george@mvista.com) to get:
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* ns = cycles * (10^6 * SC / cpu_khz) / SC
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* ns = cycles * cyc2ns_scale / SC
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*
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* And since SC is a constant power of two, we can convert the div
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* into a shift.
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*
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* We can use khz divisor instead of mhz to keep a better percision, since
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* cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
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* (mathieu.desnoyers@polymtl.ca)
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*
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* -johnstul@us.ibm.com "math is hard, lets go shopping!"
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*/
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static unsigned long cyc2ns_scale;
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#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
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static inline void set_cyc2ns_scale(unsigned long cpu_khz)
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{
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cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
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}
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static inline unsigned long long cycles_2_ns(unsigned long long cyc)
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{
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return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
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}
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static int count2; /* counter for mark_offset_tsc() */
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/* Cached *multiplier* to convert TSC counts to microseconds.
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* (see the equation below).
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* Equal to 2^32 * (1 / (clocks per usec) ).
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* Initialized in time_init.
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*/
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static unsigned long fast_gettimeoffset_quotient;
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static unsigned long get_offset_tsc(void)
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{
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register unsigned long eax, edx;
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/* Read the Time Stamp Counter */
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rdtsc(eax,edx);
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/* .. relative to previous jiffy (32 bits is enough) */
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eax -= last_tsc_low; /* tsc_low delta */
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/*
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* Time offset = (tsc_low delta) * fast_gettimeoffset_quotient
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* = (tsc_low delta) * (usecs_per_clock)
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* = (tsc_low delta) * (usecs_per_jiffy / clocks_per_jiffy)
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*
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* Using a mull instead of a divl saves up to 31 clock cycles
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* in the critical path.
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*/
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__asm__("mull %2"
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:"=a" (eax), "=d" (edx)
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:"rm" (fast_gettimeoffset_quotient),
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"0" (eax));
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/* our adjusted time offset in microseconds */
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return delay_at_last_interrupt + edx;
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}
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static unsigned long long monotonic_clock_tsc(void)
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{
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unsigned long long last_offset, this_offset, base;
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unsigned seq;
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/* atomically read monotonic base & last_offset */
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do {
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seq = read_seqbegin(&monotonic_lock);
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last_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low;
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base = monotonic_base;
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} while (read_seqretry(&monotonic_lock, seq));
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/* Read the Time Stamp Counter */
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rdtscll(this_offset);
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/* return the value in ns */
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return base + cycles_2_ns(this_offset - last_offset);
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}
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/*
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* Scheduler clock - returns current time in nanosec units.
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*/
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unsigned long long sched_clock(void)
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{
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unsigned long long this_offset;
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/*
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* In the NUMA case we dont use the TSC as they are not
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* synchronized across all CPUs.
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*/
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#ifndef CONFIG_NUMA
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if (!use_tsc)
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#endif
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/* no locking but a rare wrong value is not a big deal */
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return jiffies_64 * (1000000000 / HZ);
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/* Read the Time Stamp Counter */
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rdtscll(this_offset);
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/* return the value in ns */
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return cycles_2_ns(this_offset);
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}
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static void delay_tsc(unsigned long loops)
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{
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unsigned long bclock, now;
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rdtscl(bclock);
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do
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{
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rep_nop();
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rdtscl(now);
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} while ((now-bclock) < loops);
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}
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#ifdef CONFIG_HPET_TIMER
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static void mark_offset_tsc_hpet(void)
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{
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unsigned long long this_offset, last_offset;
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unsigned long offset, temp, hpet_current;
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write_seqlock(&monotonic_lock);
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last_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low;
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/*
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* It is important that these two operations happen almost at
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* the same time. We do the RDTSC stuff first, since it's
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* faster. To avoid any inconsistencies, we need interrupts
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* disabled locally.
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*/
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/*
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* Interrupts are just disabled locally since the timer irq
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* has the SA_INTERRUPT flag set. -arca
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*/
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/* read Pentium cycle counter */
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hpet_current = hpet_readl(HPET_COUNTER);
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rdtsc(last_tsc_low, last_tsc_high);
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/* lost tick compensation */
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offset = hpet_readl(HPET_T0_CMP) - hpet_tick;
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if (unlikely(((offset - hpet_last) > hpet_tick) && (hpet_last != 0))
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&& detect_lost_ticks) {
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int lost_ticks = (offset - hpet_last) / hpet_tick;
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jiffies_64 += lost_ticks;
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}
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hpet_last = hpet_current;
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/* update the monotonic base value */
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this_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low;
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monotonic_base += cycles_2_ns(this_offset - last_offset);
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write_sequnlock(&monotonic_lock);
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/* calculate delay_at_last_interrupt */
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/*
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* Time offset = (hpet delta) * ( usecs per HPET clock )
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* = (hpet delta) * ( usecs per tick / HPET clocks per tick)
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* = (hpet delta) * ( hpet_usec_quotient ) / (2^32)
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* Where,
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* hpet_usec_quotient = (2^32 * usecs per tick)/HPET clocks per tick
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*/
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delay_at_last_interrupt = hpet_current - offset;
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ASM_MUL64_REG(temp, delay_at_last_interrupt,
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hpet_usec_quotient, delay_at_last_interrupt);
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}
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#endif
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#ifdef CONFIG_CPU_FREQ
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#include <linux/workqueue.h>
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static unsigned int cpufreq_delayed_issched = 0;
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static unsigned int cpufreq_init = 0;
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static struct work_struct cpufreq_delayed_get_work;
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static void handle_cpufreq_delayed_get(void *v)
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{
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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cpufreq_get(cpu);
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}
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cpufreq_delayed_issched = 0;
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}
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/* if we notice lost ticks, schedule a call to cpufreq_get() as it tries
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* to verify the CPU frequency the timing core thinks the CPU is running
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* at is still correct.
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*/
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static inline void cpufreq_delayed_get(void)
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{
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if (cpufreq_init && !cpufreq_delayed_issched) {
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cpufreq_delayed_issched = 1;
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printk(KERN_DEBUG "Losing some ticks... checking if CPU frequency changed.\n");
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schedule_work(&cpufreq_delayed_get_work);
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}
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}
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/* If the CPU frequency is scaled, TSC-based delays will need a different
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* loops_per_jiffy value to function properly.
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*/
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static unsigned int ref_freq = 0;
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static unsigned long loops_per_jiffy_ref = 0;
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#ifndef CONFIG_SMP
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static unsigned long fast_gettimeoffset_ref = 0;
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static unsigned int cpu_khz_ref = 0;
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#endif
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static int
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time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct cpufreq_freqs *freq = data;
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if (val != CPUFREQ_RESUMECHANGE)
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write_seqlock_irq(&xtime_lock);
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if (!ref_freq) {
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if (!freq->old){
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ref_freq = freq->new;
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goto end;
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}
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ref_freq = freq->old;
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loops_per_jiffy_ref = cpu_data[freq->cpu].loops_per_jiffy;
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#ifndef CONFIG_SMP
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fast_gettimeoffset_ref = fast_gettimeoffset_quotient;
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cpu_khz_ref = cpu_khz;
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#endif
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}
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if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
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(val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
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(val == CPUFREQ_RESUMECHANGE)) {
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if (!(freq->flags & CPUFREQ_CONST_LOOPS))
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cpu_data[freq->cpu].loops_per_jiffy = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
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#ifndef CONFIG_SMP
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if (cpu_khz)
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cpu_khz = cpufreq_scale(cpu_khz_ref, ref_freq, freq->new);
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if (use_tsc) {
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if (!(freq->flags & CPUFREQ_CONST_LOOPS)) {
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fast_gettimeoffset_quotient = cpufreq_scale(fast_gettimeoffset_ref, freq->new, ref_freq);
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set_cyc2ns_scale(cpu_khz);
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}
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}
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#endif
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}
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end:
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if (val != CPUFREQ_RESUMECHANGE)
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write_sequnlock_irq(&xtime_lock);
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return 0;
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}
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static struct notifier_block time_cpufreq_notifier_block = {
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.notifier_call = time_cpufreq_notifier
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};
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static int __init cpufreq_tsc(void)
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{
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int ret;
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INIT_WORK(&cpufreq_delayed_get_work, handle_cpufreq_delayed_get, NULL);
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ret = cpufreq_register_notifier(&time_cpufreq_notifier_block,
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CPUFREQ_TRANSITION_NOTIFIER);
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if (!ret)
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cpufreq_init = 1;
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return ret;
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}
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core_initcall(cpufreq_tsc);
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#else /* CONFIG_CPU_FREQ */
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static inline void cpufreq_delayed_get(void) { return; }
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#endif
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int recalibrate_cpu_khz(void)
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{
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#ifndef CONFIG_SMP
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unsigned int cpu_khz_old = cpu_khz;
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if (cpu_has_tsc) {
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local_irq_disable();
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init_cpu_khz();
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local_irq_enable();
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cpu_data[0].loops_per_jiffy =
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cpufreq_scale(cpu_data[0].loops_per_jiffy,
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cpu_khz_old,
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cpu_khz);
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return 0;
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} else
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return -ENODEV;
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#else
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return -ENODEV;
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#endif
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}
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EXPORT_SYMBOL(recalibrate_cpu_khz);
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static void mark_offset_tsc(void)
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{
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unsigned long lost,delay;
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unsigned long delta = last_tsc_low;
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int count;
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int countmp;
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static int count1 = 0;
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unsigned long long this_offset, last_offset;
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static int lost_count = 0;
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write_seqlock(&monotonic_lock);
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last_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low;
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/*
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* It is important that these two operations happen almost at
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* the same time. We do the RDTSC stuff first, since it's
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* faster. To avoid any inconsistencies, we need interrupts
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* disabled locally.
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*/
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/*
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* Interrupts are just disabled locally since the timer irq
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* has the SA_INTERRUPT flag set. -arca
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*/
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/* read Pentium cycle counter */
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rdtsc(last_tsc_low, last_tsc_high);
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spin_lock(&i8253_lock);
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outb_p(0x00, PIT_MODE); /* latch the count ASAP */
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count = inb_p(PIT_CH0); /* read the latched count */
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count |= inb(PIT_CH0) << 8;
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/*
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* VIA686a test code... reset the latch if count > max + 1
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* from timer_pit.c - cjb
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*/
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if (count > LATCH) {
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outb_p(0x34, PIT_MODE);
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outb_p(LATCH & 0xff, PIT_CH0);
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outb(LATCH >> 8, PIT_CH0);
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count = LATCH - 1;
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}
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spin_unlock(&i8253_lock);
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if (pit_latch_buggy) {
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/* get center value of last 3 time lutch */
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if ((count2 >= count && count >= count1)
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|| (count1 >= count && count >= count2)) {
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count2 = count1; count1 = count;
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} else if ((count1 >= count2 && count2 >= count)
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|| (count >= count2 && count2 >= count1)) {
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countmp = count;count = count2;
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count2 = count1;count1 = countmp;
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} else {
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count2 = count1; count1 = count; count = count1;
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}
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}
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/* lost tick compensation */
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delta = last_tsc_low - delta;
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{
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register unsigned long eax, edx;
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eax = delta;
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__asm__("mull %2"
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:"=a" (eax), "=d" (edx)
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:"rm" (fast_gettimeoffset_quotient),
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"0" (eax));
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delta = edx;
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}
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delta += delay_at_last_interrupt;
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lost = delta/(1000000/HZ);
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delay = delta%(1000000/HZ);
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if (lost >= 2 && detect_lost_ticks) {
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jiffies_64 += lost-1;
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/* sanity check to ensure we're not always losing ticks */
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if (lost_count++ > 100) {
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printk(KERN_WARNING "Losing too many ticks!\n");
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printk(KERN_WARNING "TSC cannot be used as a timesource. \n");
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printk(KERN_WARNING "Possible reasons for this are:\n");
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printk(KERN_WARNING " You're running with Speedstep,\n");
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printk(KERN_WARNING " You don't have DMA enabled for your hard disk (see hdparm),\n");
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printk(KERN_WARNING " Incorrect TSC synchronization on an SMP system (see dmesg).\n");
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printk(KERN_WARNING "Falling back to a sane timesource now.\n");
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clock_fallback();
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}
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/* ... but give the TSC a fair chance */
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if (lost_count > 25)
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cpufreq_delayed_get();
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} else
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lost_count = 0;
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/* update the monotonic base value */
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this_offset = ((unsigned long long)last_tsc_high<<32)|last_tsc_low;
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monotonic_base += cycles_2_ns(this_offset - last_offset);
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write_sequnlock(&monotonic_lock);
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/* calculate delay_at_last_interrupt */
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count = ((LATCH-1) - count) * TICK_SIZE;
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delay_at_last_interrupt = (count + LATCH/2) / LATCH;
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/* catch corner case where tick rollover occured
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* between tsc and pit reads (as noted when
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* usec delta is > 90% # of usecs/tick)
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*/
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if (lost && abs(delay - delay_at_last_interrupt) > (900000/HZ))
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jiffies_64++;
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}
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static int __init init_tsc(char* override)
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{
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/* check clock override */
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if (override[0] && strncmp(override,"tsc",3)) {
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#ifdef CONFIG_HPET_TIMER
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if (is_hpet_enabled()) {
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printk(KERN_ERR "Warning: clock= override failed. Defaulting to tsc\n");
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} else
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#endif
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{
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return -ENODEV;
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}
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}
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/*
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* If we have APM enabled or the CPU clock speed is variable
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* (CPU stops clock on HLT or slows clock to save power)
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* then the TSC timestamps may diverge by up to 1 jiffy from
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* 'real time' but nothing will break.
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* The most frequent case is that the CPU is "woken" from a halt
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* state by the timer interrupt itself, so we get 0 error. In the
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* rare cases where a driver would "wake" the CPU and request a
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* timestamp, the maximum error is < 1 jiffy. But timestamps are
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* still perfectly ordered.
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* Note that the TSC counter will be reset if APM suspends
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* to disk; this won't break the kernel, though, 'cuz we're
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|
* smart. See arch/i386/kernel/apm.c.
|
|
*/
|
|
/*
|
|
* Firstly we have to do a CPU check for chips with
|
|
* a potentially buggy TSC. At this point we haven't run
|
|
* the ident/bugs checks so we must run this hook as it
|
|
* may turn off the TSC flag.
|
|
*
|
|
* NOTE: this doesn't yet handle SMP 486 machines where only
|
|
* some CPU's have a TSC. Thats never worked and nobody has
|
|
* moaned if you have the only one in the world - you fix it!
|
|
*/
|
|
|
|
count2 = LATCH; /* initialize counter for mark_offset_tsc() */
|
|
|
|
if (cpu_has_tsc) {
|
|
unsigned long tsc_quotient;
|
|
#ifdef CONFIG_HPET_TIMER
|
|
if (is_hpet_enabled() && hpet_use_timer) {
|
|
unsigned long result, remain;
|
|
printk("Using TSC for gettimeofday\n");
|
|
tsc_quotient = calibrate_tsc_hpet(NULL);
|
|
timer_tsc.mark_offset = &mark_offset_tsc_hpet;
|
|
/*
|
|
* Math to calculate hpet to usec multiplier
|
|
* Look for the comments at get_offset_tsc_hpet()
|
|
*/
|
|
ASM_DIV64_REG(result, remain, hpet_tick,
|
|
0, KERNEL_TICK_USEC);
|
|
if (remain > (hpet_tick >> 1))
|
|
result++; /* rounding the result */
|
|
|
|
hpet_usec_quotient = result;
|
|
} else
|
|
#endif
|
|
{
|
|
tsc_quotient = calibrate_tsc();
|
|
}
|
|
|
|
if (tsc_quotient) {
|
|
fast_gettimeoffset_quotient = tsc_quotient;
|
|
use_tsc = 1;
|
|
/*
|
|
* We could be more selective here I suspect
|
|
* and just enable this for the next intel chips ?
|
|
*/
|
|
/* report CPU clock rate in Hz.
|
|
* The formula is (10^6 * 2^32) / (2^32 * 1 / (clocks/us)) =
|
|
* clock/second. Our precision is about 100 ppm.
|
|
*/
|
|
{ unsigned long eax=0, edx=1000;
|
|
__asm__("divl %2"
|
|
:"=a" (cpu_khz), "=d" (edx)
|
|
:"r" (tsc_quotient),
|
|
"0" (eax), "1" (edx));
|
|
printk("Detected %u.%03u MHz processor.\n",
|
|
cpu_khz / 1000, cpu_khz % 1000);
|
|
}
|
|
set_cyc2ns_scale(cpu_khz);
|
|
return 0;
|
|
}
|
|
}
|
|
return -ENODEV;
|
|
}
|
|
|
|
static int tsc_resume(void)
|
|
{
|
|
write_seqlock(&monotonic_lock);
|
|
/* Assume this is the last mark offset time */
|
|
rdtsc(last_tsc_low, last_tsc_high);
|
|
#ifdef CONFIG_HPET_TIMER
|
|
if (is_hpet_enabled() && hpet_use_timer)
|
|
hpet_last = hpet_readl(HPET_COUNTER);
|
|
#endif
|
|
write_sequnlock(&monotonic_lock);
|
|
return 0;
|
|
}
|
|
|
|
#ifndef CONFIG_X86_TSC
|
|
/* disable flag for tsc. Takes effect by clearing the TSC cpu flag
|
|
* in cpu/common.c */
|
|
static int __init tsc_setup(char *str)
|
|
{
|
|
tsc_disable = 1;
|
|
return 1;
|
|
}
|
|
#else
|
|
static int __init tsc_setup(char *str)
|
|
{
|
|
printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
|
|
"cannot disable TSC.\n");
|
|
return 1;
|
|
}
|
|
#endif
|
|
__setup("notsc", tsc_setup);
|
|
|
|
|
|
|
|
/************************************************************/
|
|
|
|
/* tsc timer_opts struct */
|
|
static struct timer_opts timer_tsc = {
|
|
.name = "tsc",
|
|
.mark_offset = mark_offset_tsc,
|
|
.get_offset = get_offset_tsc,
|
|
.monotonic_clock = monotonic_clock_tsc,
|
|
.delay = delay_tsc,
|
|
.read_timer = read_timer_tsc,
|
|
.resume = tsc_resume,
|
|
};
|
|
|
|
struct init_timer_opts __initdata timer_tsc_init = {
|
|
.init = init_tsc,
|
|
.opts = &timer_tsc,
|
|
};
|