161 lines
5.8 KiB
C
161 lines
5.8 KiB
C
/*
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* Miscellaneous IOCTL commands for Dynamic Power Management Controller Driver
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*
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* Copyright (C) 2004-2009 Analog Device Inc.
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*
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* Licensed under the GPL-2
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*/
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#ifndef _BLACKFIN_DPMC_H_
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#define _BLACKFIN_DPMC_H_
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/* PLL_CTL Masks */
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#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
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#define PLL_OFF 0x0002 /* PLL Not Powered */
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#define STOPCK 0x0008 /* Core Clock Off */
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#define PDWN 0x0020 /* Enter Deep Sleep Mode */
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#ifdef __ADSPBF539__
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# define IN_DELAY 0x0014 /* Add 200ps Delay To EBIU Input Latches */
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# define OUT_DELAY 0x00C0 /* Add 200ps Delay To EBIU Output Signals */
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#else
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# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
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# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
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#endif
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#define BYPASS 0x0100 /* Bypass the PLL */
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#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
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#define SPORT_HYST 0x8000 /* Enable Additional Hysteresis on SPORT Input Pins */
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#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
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/* PLL_DIV Masks */
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#define SSEL 0x000F /* System Select */
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#define CSEL 0x0030 /* Core Select */
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#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
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#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
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#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
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#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
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#define CCLK_DIV1 CSEL_DIV1
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#define CCLK_DIV2 CSEL_DIV2
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#define CCLK_DIV4 CSEL_DIV4
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#define CCLK_DIV8 CSEL_DIV8
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#define SET_SSEL(x) ((x) & 0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
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#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
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/* PLL_STAT Masks */
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#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
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#define FULL_ON 0x0002 /* Processor In Full On Mode */
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#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
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#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
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#define RTCWS 0x0400 /* RTC/Reset Wake-Up Status */
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#define CANWS 0x0800 /* CAN Wake-Up Status */
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#define USBWS 0x2000 /* USB Wake-Up Status */
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#define KPADWS 0x4000 /* Keypad Wake-Up Status */
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#define ROTWS 0x8000 /* Rotary Wake-Up Status */
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#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
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/* VR_CTL Masks */
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#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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#define FREQ 0x3000 /* Switching Oscillator Frequency For Regulator */
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#define FREQ_1000 0x3000 /* Switching Frequency Is 1 MHz */
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#else
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#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
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#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
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#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
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#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
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#endif
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#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
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#define GAIN 0x000C /* Voltage Level Gain */
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#define GAIN_5 0x0000 /* GAIN = 5 */
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#define GAIN_10 0x0004 /* GAIN = 1 */
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#define GAIN_20 0x0008 /* GAIN = 2 */
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#define GAIN_50 0x000C /* GAIN = 5 */
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#define VLEV 0x00F0 /* Internal Voltage Level */
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#ifdef __ADSPBF52x__
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#define VLEV_085 0x0040 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
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#define VLEV_090 0x0050 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
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#define VLEV_095 0x0060 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
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#define VLEV_100 0x0070 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
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#define VLEV_105 0x0080 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
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#define VLEV_110 0x0090 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
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#define VLEV_115 0x00A0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
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#define VLEV_120 0x00B0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
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#else
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#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
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#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
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#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
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#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
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#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
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#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
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#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
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#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
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#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
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#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
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#endif
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#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
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#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
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#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
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#define GPWE 0x0400 /* General-Purpose Wake-Up Enable */
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#define MXVRWE 0x0400 /* Enable MXVR Wakeup From Hibernate */
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#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
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#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
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#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
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#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
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#if defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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#define USBWE 0x0200 /* Enable USB Wakeup From Hibernate */
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#else
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#define USBWE 0x0800 /* Enable USB Wakeup From Hibernate */
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#endif
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#ifndef __ASSEMBLY__
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void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
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void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
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void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
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void do_hibernate(int wakeup);
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void set_dram_srfs(void);
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void unset_dram_srfs(void);
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#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
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struct bfin_dpmc_platform_data {
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const unsigned int *tuple_tab;
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unsigned short tabsize;
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unsigned short vr_settling_time; /* in us */
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};
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#else
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#define PM_PUSH(x) \
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R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
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[--SP] = R0;\
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#define PM_POP(x) \
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R0 = [SP++];\
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[P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
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#define PM_SYS_PUSH(x) \
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R0 = [P0 + (x - PLL_CTL)];\
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[--SP] = R0;\
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#define PM_SYS_POP(x) \
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R0 = [SP++];\
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[P0 + (x - PLL_CTL)] = R0;\
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#define PM_SYS_PUSH16(x) \
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R0 = w[P0 + (x - PLL_CTL)];\
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[--SP] = R0;\
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#define PM_SYS_POP16(x) \
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R0 = [SP++];\
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w[P0 + (x - PLL_CTL)] = R0;\
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#endif
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#endif /*_BLACKFIN_DPMC_H_*/
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