28baebae73
Make the FRV arch use virtual interrupt disablement because accesses to the processor status register (PSR) are relatively slow and because we will soon have the need to deal with multiple interrupt controls at the same time (separate h/w and inter-core interrupts). The way this is done is to dedicate one of the four integer condition code registers (ICC2) to maintaining a virtual interrupt disablement state whilst inside the kernel. This uses the ICC2.Z flag (Zero) to indicate whether the interrupts are virtually disabled and the ICC2.C flag (Carry) to indicate whether the interrupts are physically disabled. ICC2.Z is set to indicate interrupts are virtually disabled. ICC2.C is set to indicate interrupts are physically enabled. Under normal running conditions Z==0 and C==1. Disabling interrupts with local_irq_disable() doesn't then actually physically disable interrupts - it merely sets ICC2.Z to 1. Should an interrupt then happen, the exception prologue will note ICC2.Z is set and branch out of line using one instruction (an unlikely BEQ). Here it will physically disable interrupts and clear ICC2.C. When it comes time to enable interrupts (local_irq_enable()), this simply clears the ICC2.Z flag and invokes a trap #2 if both Z and C flags are clear (the HI integer condition). This can be done with the TIHI conditional trap instruction. The trap then physically reenables interrupts and sets ICC2.C again. Upon returning the interrupt will be taken as interrupts will then be enabled. Note that whilst processing the trap, the whole exceptions system is disabled, and so an interrupt can't happen till it returns. If no pending interrupt had happened, ICC2.C would still be set, the HI condition would not be fulfilled, and no trap will happen. Saving interrupts (local_irq_save) is simply a matter of pulling the ICC2.Z flag out of the CCR register, shifting it down and masking it off. This gives a result of 0 if interrupts were enabled and 1 if they weren't. Restoring interrupts (local_irq_restore) is then a matter of taking the saved value mentioned previously and XOR'ing it against 1. If it was one, the result will be zero, and if it was zero the result will be non-zero. This result is then used to affect the ICC2.Z flag directly (it is a condition code flag after all). An XOR instruction does not affect the Carry flag, and so that bit of state is unchanged. The two flags can then be sampled to see if they're both zero using the trap (TIHI) as for the unconditional reenablement (local_irq_enable). This patch also: (1) Modifies the debugging stub (break.S) to handle single-stepping crossing into the trap #2 handler and into virtually disabled interrupts. (2) Removes superseded fixup pointers from the second instructions in the trap tables (there's no a separate fixup table for this). (3) Declares the trap #3 vector for use in .org directives in the trap table. (4) Moves irq_enter() and irq_exit() in do_IRQ() to avoid problems with virtual interrupt handling, and removes the duplicate code that has now been folded into irq_exit() (softirq and preemption handling). (5) Tells the compiler in the arch Makefile that ICC2 is now reserved. (6) Documents the in-kernel ABI, including the virtual interrupts. (7) Renames the old irq management functions to different names. Signed-off-by: David Howells <dhowells@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
325 lines
9.7 KiB
ArmAsm
325 lines
9.7 KiB
ArmAsm
/* entry-table.S: main trap vector tables and exception jump table
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*
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* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/sys.h>
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <asm/spr-regs.h>
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###############################################################################
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#
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# Declare the main trap and vector tables
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#
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# There are six tables:
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#
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# (1) The trap table for debug mode
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# (2) The trap table for kernel mode
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# (3) The trap table for user mode
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#
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# The CPU jumps to an appropriate slot in the appropriate table to perform
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# exception processing. We have three different tables for the three
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# different CPU modes because there is no hardware differentiation between
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# stack pointers for these three modes, and so we have to invent one when
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# crossing mode boundaries.
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#
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# (4) The exception handler vector table
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#
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# The user and kernel trap tables use the same prologue for normal
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# exception processing. The prologue then jumps to the handler in this
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# table, as indexed by the exception ID from the TBR.
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#
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# (5) The fixup table for kernel-trap single-step
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# (6) The fixup table for user-trap single-step
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#
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# Due to the way single-stepping works on this CPU (single-step is not
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# disabled when crossing exception boundaries, only when in debug mode),
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# we have to catch the single-step event in break.S and jump to the fixup
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# routine pointed to by this table.
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#
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# The linker script places the user mode and kernel mode trap tables on to
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# the same 8Kb page, so that break.S can be more efficient when performing
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# single-step bypass management
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#
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###############################################################################
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# trap table for entry from debug mode
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.section .trap.break,"ax"
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.balign 256*16
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.globl __entry_breaktrap_table
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__entry_breaktrap_table:
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# trap table for entry from user mode
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.section .trap.user,"ax"
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.balign 256*16
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.globl __entry_usertrap_table
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__entry_usertrap_table:
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# trap table for entry from kernel mode
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.section .trap.kernel,"ax"
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.balign 256*16
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.globl __entry_kerneltrap_table
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__entry_kerneltrap_table:
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# exception handler jump table
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.section .trap.vector,"ax"
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.balign 256*4
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.globl __entry_vector_table
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__entry_vector_table:
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# trap fixup table for single-stepping in user mode
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.section .trap.fixup.user,"a"
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.balign 256*4
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.globl __break_usertrap_fixup_table
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__break_usertrap_fixup_table:
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# trap fixup table for single-stepping in user mode
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.section .trap.fixup.kernel,"a"
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.balign 256*4
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.globl __break_kerneltrap_fixup_table
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__break_kerneltrap_fixup_table:
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# handler declaration for a sofware or program interrupt
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.macro VECTOR_SOFTPROG tbr_tt, vec
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.section .trap.user
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.org \tbr_tt
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bra __entry_uspace_softprog_interrupt
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.section .trap.fixup.user
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.org \tbr_tt >> 2
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.long __break_step_uspace_softprog_interrupt
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.section .trap.kernel
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.org \tbr_tt
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bra __entry_kernel_softprog_interrupt
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.section .trap.fixup.kernel
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.org \tbr_tt >> 2
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.long __break_step_kernel_softprog_interrupt
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.section .trap.vector
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.org \tbr_tt >> 2
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.long \vec
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.endm
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# handler declaration for a maskable external interrupt
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.macro VECTOR_IRQ tbr_tt, vec
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.section .trap.user
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.org \tbr_tt
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bra __entry_uspace_external_interrupt
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.section .trap.fixup.user
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.org \tbr_tt >> 2
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.long __break_step_uspace_external_interrupt
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.section .trap.kernel
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.org \tbr_tt
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# deal with virtual interrupt disablement
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beq icc2,#0,__entry_kernel_external_interrupt_virtually_disabled
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bra __entry_kernel_external_interrupt
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.section .trap.fixup.kernel
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.org \tbr_tt >> 2
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.long __break_step_kernel_external_interrupt
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.section .trap.vector
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.org \tbr_tt >> 2
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.long \vec
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.endm
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# handler declaration for an NMI external interrupt
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.macro VECTOR_NMI tbr_tt, vec
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.section .trap.user
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.org \tbr_tt
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break
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break
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break
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break
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.section .trap.kernel
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.org \tbr_tt
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break
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break
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break
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break
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.section .trap.vector
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.org \tbr_tt >> 2
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.long \vec
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.endm
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# handler declaration for an MMU only sofware or program interrupt
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.macro VECTOR_SP_MMU tbr_tt, vec
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#ifdef CONFIG_MMU
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VECTOR_SOFTPROG \tbr_tt, \vec
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#else
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VECTOR_NMI \tbr_tt, 0
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#endif
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.endm
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###############################################################################
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#
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# specification of the vectors
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# - note: each macro inserts code into multiple sections
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#
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###############################################################################
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VECTOR_SP_MMU TBR_TT_INSTR_MMU_MISS, __entry_insn_mmu_miss
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VECTOR_SOFTPROG TBR_TT_INSTR_ACC_ERROR, __entry_insn_access_error
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VECTOR_SOFTPROG TBR_TT_INSTR_ACC_EXCEP, __entry_insn_access_exception
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VECTOR_SOFTPROG TBR_TT_PRIV_INSTR, __entry_privileged_instruction
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VECTOR_SOFTPROG TBR_TT_ILLEGAL_INSTR, __entry_illegal_instruction
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VECTOR_SOFTPROG TBR_TT_FP_EXCEPTION, __entry_media_exception
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VECTOR_SOFTPROG TBR_TT_MP_EXCEPTION, __entry_media_exception
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VECTOR_SOFTPROG TBR_TT_DATA_ACC_ERROR, __entry_data_access_error
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VECTOR_SP_MMU TBR_TT_DATA_MMU_MISS, __entry_data_mmu_miss
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VECTOR_SOFTPROG TBR_TT_DATA_ACC_EXCEP, __entry_data_access_exception
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VECTOR_SOFTPROG TBR_TT_DATA_STR_ERROR, __entry_data_store_error
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VECTOR_SOFTPROG TBR_TT_DIVISION_EXCEP, __entry_division_exception
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#ifdef CONFIG_MMU
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.section .trap.user
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.org TBR_TT_INSTR_TLB_MISS
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.globl __trap_user_insn_tlb_miss
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__trap_user_insn_tlb_miss:
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movsg ear0,gr28 /* faulting address */
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movsg scr0,gr31 /* get mapped PTD coverage start address */
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xor.p gr28,gr31,gr31 /* compare addresses */
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bra __entry_user_insn_tlb_miss
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.org TBR_TT_DATA_TLB_MISS
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.globl __trap_user_data_tlb_miss
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__trap_user_data_tlb_miss:
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movsg ear0,gr28 /* faulting address */
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movsg scr1,gr31 /* get mapped PTD coverage start address */
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xor.p gr28,gr31,gr31 /* compare addresses */
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bra __entry_user_data_tlb_miss
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.section .trap.kernel
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.org TBR_TT_INSTR_TLB_MISS
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.globl __trap_kernel_insn_tlb_miss
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__trap_kernel_insn_tlb_miss:
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movsg ear0,gr29 /* faulting address */
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movsg scr0,gr31 /* get mapped PTD coverage start address */
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xor.p gr29,gr31,gr31 /* compare addresses */
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bra __entry_kernel_insn_tlb_miss
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.org TBR_TT_DATA_TLB_MISS
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.globl __trap_kernel_data_tlb_miss
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__trap_kernel_data_tlb_miss:
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movsg ear0,gr29 /* faulting address */
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movsg scr1,gr31 /* get mapped PTD coverage start address */
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xor.p gr29,gr31,gr31 /* compare addresses */
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bra __entry_kernel_data_tlb_miss
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.section .trap.fixup.user
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.org TBR_TT_INSTR_TLB_MISS >> 2
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.globl __trap_fixup_user_insn_tlb_miss
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__trap_fixup_user_insn_tlb_miss:
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.long __break_user_insn_tlb_miss
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.org TBR_TT_DATA_TLB_MISS >> 2
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.globl __trap_fixup_user_data_tlb_miss
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__trap_fixup_user_data_tlb_miss:
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.long __break_user_data_tlb_miss
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.section .trap.fixup.kernel
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.org TBR_TT_INSTR_TLB_MISS >> 2
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.globl __trap_fixup_kernel_insn_tlb_miss
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__trap_fixup_kernel_insn_tlb_miss:
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.long __break_kernel_insn_tlb_miss
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.org TBR_TT_DATA_TLB_MISS >> 2
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.globl __trap_fixup_kernel_data_tlb_miss
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__trap_fixup_kernel_data_tlb_miss:
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.long __break_kernel_data_tlb_miss
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.section .trap.vector
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.org TBR_TT_INSTR_TLB_MISS >> 2
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.long __entry_insn_mmu_fault
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.org TBR_TT_DATA_TLB_MISS >> 2
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.long __entry_data_mmu_fault
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#endif
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VECTOR_SP_MMU TBR_TT_DATA_DAT_EXCEP, __entry_data_dat_fault
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VECTOR_NMI TBR_TT_DECREMENT_TIMER, __entry_do_NMI
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VECTOR_SOFTPROG TBR_TT_COMPOUND_EXCEP, __entry_compound_exception
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VECTOR_IRQ TBR_TT_INTERRUPT_1, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_2, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_3, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_4, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_5, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_6, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_7, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_8, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_9, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_10, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_11, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_12, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_13, __entry_do_IRQ
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VECTOR_IRQ TBR_TT_INTERRUPT_14, __entry_do_IRQ
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VECTOR_NMI TBR_TT_INTERRUPT_15, __entry_do_NMI
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# miscellaneous user mode entry points
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.section .trap.user
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.org TBR_TT_TRAP0
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.rept 127
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bra __entry_uspace_softprog_interrupt
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.long 0,0,0
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.endr
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.org TBR_TT_BREAK
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bra __entry_break
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.long 0,0,0
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.section .trap.fixup.user
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.org TBR_TT_TRAP0 >> 2
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.rept 127
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.long __break_step_uspace_softprog_interrupt
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.endr
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.org TBR_TT_BREAK >> 2
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.long 0
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# miscellaneous kernel mode entry points
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.section .trap.kernel
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.org TBR_TT_TRAP0
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bra __entry_kernel_softprog_interrupt
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.org TBR_TT_TRAP1
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bra __entry_kernel_softprog_interrupt
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# trap #2 in kernel - reenable interrupts
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.org TBR_TT_TRAP2
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bra __entry_kernel_external_interrupt_virtual_reenable
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# miscellaneous kernel traps
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.org TBR_TT_TRAP3
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.rept 124
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bra __entry_kernel_softprog_interrupt
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.long 0,0,0
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.endr
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.org TBR_TT_BREAK
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bra __entry_break
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.long 0,0,0
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.section .trap.fixup.kernel
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.org TBR_TT_TRAP0 >> 2
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.long __break_step_kernel_softprog_interrupt
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.long __break_step_kernel_softprog_interrupt
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.long __break_step_kernel_external_interrupt_virtual_reenable
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.rept 124
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.long __break_step_kernel_softprog_interrupt
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.endr
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.org TBR_TT_BREAK >> 2
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.long 0
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# miscellaneous debug mode entry points
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.section .trap.break
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.org TBR_TT_BREAK
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movsg bpcsr,gr30
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jmpl @(gr30,gr0)
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# miscellaneous vectors
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.section .trap.vector
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.org TBR_TT_TRAP0 >> 2
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.long system_call
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.rept 126
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.long __entry_unsupported_trap
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.endr
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.org TBR_TT_BREAK >> 2
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.long __entry_debug_exception
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