2277ab4a1d
This inverts the delayed dcache flush a bit to be more in line with other platforms. At the same time this also gives us the ability to do some more optimizations and cleanup. Now that the update_mmu_cache() callsite only tests for the bit, the implementation can gradually be split out and made generic, rather than relying on special implementations for each of the peculiar CPU types. SH7705 in 32kB mode and SH-4 still need slightly different handling, but this is something that can remain isolated in the varying page copy/clear routines. On top of that, SH-X3 is dcache coherent, so there is no need to bother with any of these tests in the PTEAEX version of update_mmu_cache(), so we kill that off too. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
44 lines
1.5 KiB
C
44 lines
1.5 KiB
C
/*
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* include/asm-sh/cpu-sh3/cacheflush.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
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#define __ASM_CPU_SH3_CACHEFLUSH_H
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#if defined(CONFIG_SH7705_CACHE_32KB)
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/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
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* SH4. Unlike the SH4 this is a unified cache so we need to do some work
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* in mmap when 'exec'ing a new binary
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*/
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#define PG_dcache_dirty PG_arch_1
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void flush_cache_all(void);
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void flush_cache_mm(struct mm_struct *mm);
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#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end);
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void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
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void flush_dcache_page(struct page *pg);
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void flush_icache_range(unsigned long start, unsigned long end);
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void flush_icache_page(struct vm_area_struct *vma, struct page *page);
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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/* SH3 has unified cache so no special action needed here */
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#define flush_cache_sigtramp(vaddr) do { } while (0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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#define p3_cache_init() do { } while (0)
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#else
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#include <cpu-common/cpu/cacheflush.h>
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#endif
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#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
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