Kumar Gala 2319f12395 powerpc/mm: e300c2/c3/c4 TLB errata workaround ... Complete workaround for DTLB errata in e300c2/c3/c4 processors. Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of the TLB. This fix implements the proposed software workaround in form of a LRW table for chosing the TLB-way. Based on patch from David Jander <david@protonic.nl> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>		2009-03-24 13:47:32 +11:00
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asm	powerpc/mm: e300c2/c3/c4 TLB errata workaround	2009-03-24 13:47:32 +11:00