189e91f5f5
The defines and typedefs (hw_interrupt_type, no_irq_type, irq_desc_t) have been kept around for migration reasons. After more than two years it's time to remove them finally. This patch cleans up one of the remaining users. When all such patches hit mainline we can remove the defines and typedefs finally. Impact: cleanup Convert the last remaining users to struct irq_chip and remove the define. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
249 lines
6.6 KiB
C
249 lines
6.6 KiB
C
/*
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* linux/arch/m32r/platforms/usrv/setup.c
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*
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* Setup routines for MITSUBISHI uServer
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*
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* Copyright (c) 2001, 2002, 2003 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto
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*/
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
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icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
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static void disable_mappi_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
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outl(data, port);
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}
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static void enable_mappi_irq(unsigned int irq)
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{
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unsigned long port, data;
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port = irq2port(irq);
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data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
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outl(data, port);
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}
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static void mask_and_ack_mappi(unsigned int irq)
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{
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disable_mappi_irq(irq);
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}
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static void end_mappi_irq(unsigned int irq)
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{
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enable_mappi_irq(irq);
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}
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static unsigned int startup_mappi_irq(unsigned int irq)
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{
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enable_mappi_irq(irq);
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return 0;
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}
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static void shutdown_mappi_irq(unsigned int irq)
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{
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unsigned long port;
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port = irq2port(irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip mappi_irq_type =
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{
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.typename = "M32700-IRQ",
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.startup = startup_mappi_irq,
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.shutdown = shutdown_mappi_irq,
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.enable = enable_mappi_irq,
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.disable = disable_mappi_irq,
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.ack = mask_and_ack_mappi,
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.end = end_mappi_irq
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};
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/*
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* Interrupt Control Unit of PLD on M32700UT (Level 2)
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*/
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#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
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#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
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(((x) - 1) * sizeof(unsigned short)))
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typedef struct {
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unsigned short icucr; /* ICU Control Register */
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} pld_icu_data_t;
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static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
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static void disable_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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}
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static void enable_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port, data;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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}
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static void mask_and_ack_m32700ut_pld(unsigned int irq)
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{
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disable_m32700ut_pld_irq(irq);
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}
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static void end_m32700ut_pld_irq(unsigned int irq)
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{
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enable_m32700ut_pld_irq(irq);
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end_mappi_irq(M32R_IRQ_INT1);
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}
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static unsigned int startup_m32700ut_pld_irq(unsigned int irq)
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{
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enable_m32700ut_pld_irq(irq);
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return 0;
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}
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static void shutdown_m32700ut_pld_irq(unsigned int irq)
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{
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unsigned long port;
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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port = pldirq2port(pldirq);
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outw(PLD_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip m32700ut_pld_irq_type =
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{
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.typename = "USRV-PLD-IRQ",
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.startup = startup_m32700ut_pld_irq,
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.shutdown = shutdown_m32700ut_pld_irq,
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.enable = enable_m32700ut_pld_irq,
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.disable = disable_m32700ut_pld_irq,
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.ack = mask_and_ack_m32700ut_pld,
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.end = end_m32700ut_pld_irq
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};
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void __init init_IRQ(void)
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{
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static int once = 0;
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int i;
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if (once)
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return;
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else
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once++;
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/* MFT2 : system timer */
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irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_MFT2].chip = &mappi_irq_type;
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irq_desc[M32R_IRQ_MFT2].action = 0;
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irq_desc[M32R_IRQ_MFT2].depth = 1;
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_mappi_irq(M32R_IRQ_MFT2);
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#if defined(CONFIG_SERIAL_M32R_SIO)
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/* SIO0_R : uart receive data */
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irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_R].chip = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO0_R].action = 0;
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irq_desc[M32R_IRQ_SIO0_R].depth = 1;
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icu_data[M32R_IRQ_SIO0_R].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO0_R);
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/* SIO0_S : uart send data */
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irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO0_S].chip = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO0_S].action = 0;
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irq_desc[M32R_IRQ_SIO0_S].depth = 1;
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icu_data[M32R_IRQ_SIO0_S].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO0_S);
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/* SIO1_R : uart receive data */
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irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_R].chip = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO1_R].action = 0;
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irq_desc[M32R_IRQ_SIO1_R].depth = 1;
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icu_data[M32R_IRQ_SIO1_R].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO1_R);
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/* SIO1_S : uart send data */
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irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
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irq_desc[M32R_IRQ_SIO1_S].chip = &mappi_irq_type;
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irq_desc[M32R_IRQ_SIO1_S].action = 0;
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irq_desc[M32R_IRQ_SIO1_S].depth = 1;
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icu_data[M32R_IRQ_SIO1_S].icucr = 0;
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disable_mappi_irq(M32R_IRQ_SIO1_S);
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#endif /* CONFIG_SERIAL_M32R_SIO */
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/* INT#67-#71: CFC#0 IREQ on PLD */
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for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
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irq_desc[PLD_IRQ_CF0 + i].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_CF0 + i].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_CF0 + i].action = 0;
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irq_desc[PLD_IRQ_CF0 + i].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
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= PLD_ICUCR_ISMOD01; /* 'L' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_CF0 + i);
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}
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#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
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/* INT#76: 16552D#0 IREQ on PLD */
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irq_desc[PLD_IRQ_UART0].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_UART0].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_UART0].action = 0;
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irq_desc[PLD_IRQ_UART0].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
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= PLD_ICUCR_ISMOD03; /* 'H' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_UART0);
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/* INT#77: 16552D#1 IREQ on PLD */
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irq_desc[PLD_IRQ_UART1].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_UART1].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_UART1].action = 0;
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irq_desc[PLD_IRQ_UART1].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
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= PLD_ICUCR_ISMOD03; /* 'H' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_UART1);
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#endif /* CONFIG_SERIAL_8250 || CONFIG_SERIAL_8250_MODULE */
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#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
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/* INT#80: AK4524 IREQ on PLD */
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irq_desc[PLD_IRQ_SNDINT].status = IRQ_DISABLED;
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irq_desc[PLD_IRQ_SNDINT].chip = &m32700ut_pld_irq_type;
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irq_desc[PLD_IRQ_SNDINT].action = 0;
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irq_desc[PLD_IRQ_SNDINT].depth = 1; /* disable nested irq */
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pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
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= PLD_ICUCR_ISMOD01; /* 'L' level sense */
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disable_m32700ut_pld_irq(PLD_IRQ_SNDINT);
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#endif /* CONFIG_IDC_AK4524 || CONFIG_IDC_AK4524_MODULE */
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/*
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* INT1# is used for UART, MMC, CF Controller in FPGA.
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* We enable it here.
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*/
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icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD11;
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enable_mappi_irq(M32R_IRQ_INT1);
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}
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