e3a078c712
DSC and VDC-M sub-block registers are not on contiguous address range. This change allows dumping the registers for each individual sub-block. Change-Id: I06dfc64562211370a0e29f6fc1134351c47722f6 Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
314 lines
7.9 KiB
C
314 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hw_mdss.h"
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#include "sde_hwio.h"
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#include "sde_hw_catalog.h"
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#include "sde_hw_dsc.h"
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#include "sde_hw_pingpong.h"
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#include "sde_dbg.h"
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#include "sde_kms.h"
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#include "sde_hw_dsc_1_2.h"
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#define DSC_COMMON_MODE 0x000
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#define DSC_ENC 0X004
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#define DSC_PICTURE 0x008
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#define DSC_SLICE 0x00C
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#define DSC_CHUNK_SIZE 0x010
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#define DSC_DELAY 0x014
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#define DSC_SCALE_INITIAL 0x018
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#define DSC_SCALE_DEC_INTERVAL 0x01C
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#define DSC_SCALE_INC_INTERVAL 0x020
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#define DSC_FIRST_LINE_BPG_OFFSET 0x024
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#define DSC_BPG_OFFSET 0x028
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#define DSC_DSC_OFFSET 0x02C
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#define DSC_FLATNESS 0x030
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#define DSC_RC_MODEL_SIZE 0x034
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#define DSC_RC 0x038
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#define DSC_RC_BUF_THRESH 0x03C
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#define DSC_RANGE_MIN_QP 0x074
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#define DSC_RANGE_MAX_QP 0x0B0
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#define DSC_RANGE_BPG_OFFSET 0x0EC
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#define DSC_CTL_BLOCK_SIZE 0x300
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#define DSC_CTL(m) \
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(((m == DSC_NONE) || (m >= DSC_MAX)) ? 0 : (0x1800 - 0x3FC * (m - 1)))
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static void sde_hw_dsc_disable(struct sde_hw_dsc *dsc)
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{
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struct sde_hw_blk_reg_map *dsc_c = &dsc->hw;
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SDE_REG_WRITE(dsc_c, DSC_COMMON_MODE, 0);
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}
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static void sde_hw_dsc_config(struct sde_hw_dsc *hw_dsc,
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struct msm_display_dsc_info *dsc, u32 mode,
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bool ich_reset_override)
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{
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u32 data;
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u32 initial_lines = dsc->initial_lines;
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struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;
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SDE_REG_WRITE(dsc_c, DSC_COMMON_MODE, mode);
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data = 0;
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if (ich_reset_override)
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data = 3 << 28;
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data |= (initial_lines << 20);
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data |= (dsc->slice_last_group_size << 18);
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/* integer bpp support only */
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data |= (dsc->config.bits_per_pixel << 8);
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data |= (dsc->config.block_pred_enable << 7);
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data |= (dsc->config.line_buf_depth << 3);
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data |= (dsc->config.simple_422 << 2);
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data |= (dsc->config.convert_rgb << 1);
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if (dsc->config.bits_per_component == 10)
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data |= BIT(0);
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SDE_REG_WRITE(dsc_c, DSC_ENC, data);
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data = dsc->config.pic_width << 16;
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data |= dsc->config.pic_height;
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SDE_REG_WRITE(dsc_c, DSC_PICTURE, data);
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data = dsc->config.slice_width << 16;
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data |= dsc->config.slice_height;
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SDE_REG_WRITE(dsc_c, DSC_SLICE, data);
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data = dsc->config.slice_chunk_size << 16;
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SDE_REG_WRITE(dsc_c, DSC_CHUNK_SIZE, data);
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data = dsc->config.initial_dec_delay << 16;
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data |= dsc->config.initial_xmit_delay;
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SDE_REG_WRITE(dsc_c, DSC_DELAY, data);
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data = dsc->config.initial_scale_value;
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SDE_REG_WRITE(dsc_c, DSC_SCALE_INITIAL, data);
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data = dsc->config.scale_decrement_interval;
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SDE_REG_WRITE(dsc_c, DSC_SCALE_DEC_INTERVAL, data);
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data = dsc->config.scale_increment_interval;
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SDE_REG_WRITE(dsc_c, DSC_SCALE_INC_INTERVAL, data);
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data = dsc->config.first_line_bpg_offset;
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SDE_REG_WRITE(dsc_c, DSC_FIRST_LINE_BPG_OFFSET, data);
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data = dsc->config.nfl_bpg_offset << 16;
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data |= dsc->config.slice_bpg_offset;
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SDE_REG_WRITE(dsc_c, DSC_BPG_OFFSET, data);
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data = dsc->config.initial_offset << 16;
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data |= dsc->config.final_offset;
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SDE_REG_WRITE(dsc_c, DSC_DSC_OFFSET, data);
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data = dsc->det_thresh_flatness << 10;
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data |= dsc->config.flatness_max_qp << 5;
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data |= dsc->config.flatness_min_qp;
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SDE_REG_WRITE(dsc_c, DSC_FLATNESS, data);
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data = dsc->config.rc_model_size;
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SDE_REG_WRITE(dsc_c, DSC_RC_MODEL_SIZE, data);
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data = dsc->config.rc_tgt_offset_low << 18;
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data |= dsc->config.rc_tgt_offset_high << 14;
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data |= dsc->config.rc_quant_incr_limit1 << 9;
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data |= dsc->config.rc_quant_incr_limit0 << 4;
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data |= dsc->config.rc_edge_factor;
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SDE_REG_WRITE(dsc_c, DSC_RC, data);
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}
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static void sde_hw_dsc_config_thresh(struct sde_hw_dsc *hw_dsc,
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struct msm_display_dsc_info *dsc)
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{
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u16 *lp;
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int i;
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struct sde_hw_blk_reg_map *dsc_c = &hw_dsc->hw;
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u32 off = 0x0;
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struct drm_dsc_rc_range_parameters *rc =
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dsc->config.rc_range_params;
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lp = dsc->config.rc_buf_thresh;
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off = DSC_RC_BUF_THRESH;
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for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) {
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SDE_REG_WRITE(dsc_c, off, *lp++);
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off += 4;
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}
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off = DSC_RANGE_MIN_QP;
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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SDE_REG_WRITE(dsc_c, off, rc[i].range_min_qp);
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off += 4;
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}
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off = DSC_RANGE_MAX_QP;
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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SDE_REG_WRITE(dsc_c, off, rc[i].range_max_qp);
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off += 4;
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}
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off = DSC_RANGE_BPG_OFFSET;
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for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
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SDE_REG_WRITE(dsc_c, off, rc[i].range_bpg_offset);
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off += 4;
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}
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}
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static void sde_hw_dsc_bind_pingpong_blk(
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struct sde_hw_dsc *hw_dsc,
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bool enable,
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const enum sde_pingpong pp)
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{
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struct sde_hw_blk_reg_map *c;
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int mux_cfg = 0xF;
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u32 dsc_ctl_offset;
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if (!hw_dsc)
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return;
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c = &hw_dsc->hw;
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dsc_ctl_offset = DSC_CTL(hw_dsc->idx);
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if (enable)
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mux_cfg = (pp - PINGPONG_0) & 0x7;
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if (dsc_ctl_offset)
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SDE_REG_WRITE(c, dsc_ctl_offset, mux_cfg);
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}
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static struct sde_dsc_cfg *_dsc_offset(enum sde_dsc dsc,
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struct sde_mdss_cfg *m,
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void __iomem *addr,
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struct sde_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->dsc_count; i++) {
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if (dsc == m->dsc[i].id) {
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b->base_off = addr;
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b->blk_off = m->dsc[i].base;
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b->length = m->dsc[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = SDE_DBG_MASK_DSC;
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return &m->dsc[i];
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}
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}
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return NULL;
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}
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static void _setup_dsc_ops(struct sde_hw_dsc_ops *ops,
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unsigned long features)
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{
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ops->dsc_disable = sde_hw_dsc_disable;
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ops->dsc_config = sde_hw_dsc_config;
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ops->dsc_config_thresh = sde_hw_dsc_config_thresh;
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if (test_bit(SDE_DSC_OUTPUT_CTRL, &features))
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ops->bind_pingpong_blk = sde_hw_dsc_bind_pingpong_blk;
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};
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static struct sde_hw_blk_ops sde_hw_ops = {
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.start = NULL,
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.stop = NULL,
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};
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struct sde_hw_dsc *sde_hw_dsc_init(enum sde_dsc idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m)
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{
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struct sde_hw_dsc *c;
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struct sde_dsc_cfg *cfg;
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u32 dsc_ctl_offset;
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int rc = -EINVAL;
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _dsc_offset(idx, m, addr, &c->hw);
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if (IS_ERR_OR_NULL(cfg)) {
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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c->idx = idx;
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c->caps = cfg;
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if (test_bit(SDE_DSC_HW_REV_1_1, &c->caps->features)) {
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_setup_dsc_ops(&c->ops, c->caps->features);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
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c->hw.blk_off,
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c->hw.blk_off + c->hw.length,
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c->hw.xin_id);
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if ((c->idx == DSC_0) &&
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test_bit(SDE_DSC_OUTPUT_CTRL, &cfg->features)) {
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dsc_ctl_offset = DSC_CTL(c->idx);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
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"dsc_ctl",
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c->hw.blk_off + dsc_ctl_offset,
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c->hw.blk_off + dsc_ctl_offset +
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DSC_CTL_BLOCK_SIZE,
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c->hw.xin_id);
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}
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} else if (test_bit(SDE_DSC_HW_REV_1_2, &c->caps->features)) {
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char blk_name[32];
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sde_dsc1_2_setup_ops(&c->ops, c->caps->features);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name,
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c->hw.blk_off,
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c->hw.blk_off + c->hw.length,
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c->hw.xin_id);
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snprintf(blk_name, sizeof(blk_name), "dsc_enc_%u",
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c->idx - DSC_0);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
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blk_name,
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c->hw.blk_off + c->caps->sblk->enc.base,
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c->hw.blk_off + c->caps->sblk->enc.base +
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c->caps->sblk->enc.len,
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c->hw.xin_id);
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snprintf(blk_name, sizeof(blk_name), "dsc_ctl_%u",
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c->idx - DSC_0);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME,
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blk_name,
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c->hw.blk_off + c->caps->sblk->ctl.base,
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c->hw.blk_off + c->caps->sblk->ctl.base +
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c->caps->sblk->ctl.len,
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c->hw.xin_id);
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} else {
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SDE_ERROR("failed to setup ops\n");
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goto blk_init_error;
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}
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rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_DSC, idx, &sde_hw_ops);
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if (rc) {
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SDE_ERROR("failed to init hw blk %d\n", rc);
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goto blk_init_error;
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}
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return c;
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blk_init_error:
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kzfree(c);
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return ERR_PTR(rc);
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}
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void sde_hw_dsc_destroy(struct sde_hw_dsc *dsc)
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{
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if (dsc)
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sde_hw_blk_destroy(&dsc->base);
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kfree(dsc);
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}
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