3f4a79d45a
Add support for HDR memory pool blocks aligned to a 4k page address. This feature must be enabled by setting the corresponding feature bit for supported targets. Change-Id: I696ffb6ce3b607741f26496d40e2296c4c5bdb4b Signed-off-by: Steve Cohen <cohens@codeaurora.org>
92 lines
3.5 KiB
C
92 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HWIO_H
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#define _SDE_HWIO_H
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#include "sde_hw_util.h"
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/**
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* MDP TOP block Register and bit fields and defines
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*/
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#define DISP_INTF_SEL 0x004
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#define INTR_EN 0x010
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#define INTR_STATUS 0x014
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#define INTR_CLEAR 0x018
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#define INTR2_EN 0x008
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#define INTR2_STATUS 0x00c
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#define INTR2_CLEAR 0x02c
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#define HIST_INTR_EN 0x01c
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#define HIST_INTR_STATUS 0x020
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#define HIST_INTR_CLEAR 0x024
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#define INTF_INTR_EN 0x1C0
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#define INTF_INTR_STATUS 0x1C4
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#define INTF_INTR_CLEAR 0x1C8
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#define SPLIT_DISPLAY_EN 0x2F4
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#define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8
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#define DSPP_IGC_COLOR0_RAM_LUTN 0x300
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#define DSPP_IGC_COLOR1_RAM_LUTN 0x304
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#define DSPP_IGC_COLOR2_RAM_LUTN 0x308
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#define PPB0_CNTL 0x330
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#define PPB0_CONFIG 0x334
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#define PPB1_CNTL 0x338
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#define PPB1_CONFIG 0x33C
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#define PPB2_CNTL 0x370
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#define PPB3_CNTL 0x374
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#define HW_EVENTS_CTL 0x37C
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#define CLK_CTRL3 0x3A8
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#define CLK_STATUS3 0x3AC
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#define CLK_CTRL4 0x3B0
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#define CLK_STATUS4 0x3B4
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#define CLK_CTRL5 0x3B8
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#define CLK_STATUS5 0x3BC
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#define CLK_CTRL7 0x3D0
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#define CLK_STATUS7 0x3D4
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#define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F0
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#define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F4
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#define INTF_SW_RESET_MASK 0x3FC
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#define HDMI_DP_CORE_SELECT 0x408
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#define MDP_OUT_CTL_0 0x410
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#define MDP_VSYNC_SEL 0x414
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#define DCE_SEL 0x450
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#define DP_DHDR_MEM_POOL_0_DATA 0x46c
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#define DP_DHDR_MEM_POOL_1_DATA 0x470
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#define DP_DHDR_MEM_POOL_0_NUM_BYTES 0x47c
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#define DP_DHDR_MEM_POOL_1_NUM_BYTES 0x480
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#define DP_DHDR_MEM_POOL_0_DATA_4K 0x1004
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#define DP_DHDR_MEM_POOL_1_DATA_4K 0x2004
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#define DP_DHDR_MEM_POOL_0_NUM_BYTES_4K 0x100c
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#define DP_DHDR_MEM_POOL_1_NUM_BYTES_4K 0x200c
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/* SDE_SCALER_QSEED3 */
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#define QSEED3_COEF_LUT_OFF 0x100
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#define QSEED3_FILTERS 5
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#define QSEED3_LUT_REGIONS 4
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#define QSEED3_CIRCULAR_LUTS 9
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#define QSEED3_SEPARABLE_LUTS 10
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#define QSEED3_LUT_SIZE 60
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#define QSEED3_DIR_LUT_SIZE (200 * sizeof(u32))
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#define QSEED3_COEF_LUT_DIR_BIT 1
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#define QSEED3_COEF_LUT_Y_CIR_BIT 2
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#define QSEED3_COEF_LUT_UV_CIR_BIT 3
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#define QSEED3_COEF_LUT_Y_SEP_BIT 4
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#define QSEED3_COEF_LUT_UV_SEP_BIT 5
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#define QSEED3_CIR_LUT_SIZE \
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(QSEED3_LUT_SIZE * QSEED3_CIRCULAR_LUTS * sizeof(u32))
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#define QSEED3_SEP_LUT_SIZE \
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(QSEED3_LUT_SIZE * QSEED3_SEPARABLE_LUTS * sizeof(u32))
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/* SDE_SCALER_QSEED3LITE */
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#define QSEED3L_COEF_LUT_OFF 0x100
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#define QSEED3LITE_FILTERS 2
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#define QSEED3L_SEPARABLE_LUTS 10
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#define QSEED3L_LUT_SIZE 33
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#define QSEED3L_SEP_LUT_SIZE \
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(QSEED3L_LUT_SIZE * QSEED3L_SEPARABLE_LUTS * sizeof(u32))
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#endif /*_SDE_HWIO_H */
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