eddae0d758
RSC is timing out while checking for power control register, increasing wait times only after a poms, removes this issue. Change-Id: I4a324eb3c87e7dfb84d9a8b0a11597327d206a74 Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org> Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
263 lines
8.3 KiB
C
263 lines
8.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_RSC_PRIV_H_
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#define _SDE_RSC_PRIV_H_
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#include <linux/kernel.h>
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#include <linux/sde_io_util.h>
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#include <linux/sde_rsc.h>
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#include <soc/qcom/tcs.h>
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#include "sde_power_handle.h"
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#define SDE_RSC_COMPATIBLE "disp_rscc"
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#define MAX_RSC_COUNT 5
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#define ALL_MODES_DISABLED 0x0
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#define ONLY_MODE_0_ENABLED 0x1
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#define ONLY_MODE_0_1_ENABLED 0x3
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#define ALL_MODES_ENABLED 0x7
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#define MAX_COUNT_SIZE_SUPPORTED 128
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#define SDE_RSC_REV_1 0x1
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#define SDE_RSC_REV_2 0x2
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#define SDE_RSC_REV_3 0x3
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#define SDE_RSC_REV_4 0x4
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#define SDE_RSC_HW_MAJOR_MINOR_STEP(major, minor, step) \
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(((major & 0xff) << 16) |\
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((minor & 0xff) << 8) | \
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(step & 0xff))
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struct sde_rsc_priv;
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/**
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* rsc_mode_req: sde rsc mode request information
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* MODE_READ: read vsync status
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* MODE_UPDATE: mode timeslot update
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* 0x0: all modes are disabled.
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* 0x1: Mode-0 is enabled and other two modes are disabled.
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* 0x3: Mode-0 & Mode-1 are enabled and mode-2 is disabled.
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* 0x7: all modes are enabled.
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*/
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enum rsc_mode_req {
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MODE_READ,
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MODE_UPDATE = 0x1,
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};
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/**
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* rsc_vsync_req: sde rsc vsync request information
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* VSYNC_READ: read vsync status
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* VSYNC_READ_VSYNC0: read value vsync0 timestamp (cast to int from u32)
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* VSYNC_ENABLE: enable rsc wrapper vsync status
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* VSYNC_DISABLE: disable rsc wrapper vsync status
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*/
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enum rsc_vsync_req {
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VSYNC_READ,
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VSYNC_READ_VSYNC0,
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VSYNC_ENABLE,
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VSYNC_DISABLE,
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};
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/**
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* struct sde_rsc_hw_ops - sde resource state coordinator hardware ops
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* @init: Initialize the sequencer, solver, qtimer,
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etc. hardware blocks on RSC.
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* @timer_update: update the static wrapper time and pdc/rsc
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backoff time.
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* @tcs_wait: Waits for TCS block OK to allow sending a
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* TCS command.
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* @hw_vsync: Enables the vsync on RSC block.
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* @tcs_use_ok: set TCS set to high to allow RSC to use it.
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* @bwi_status: It updates the BW increase/decrease status.
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* @is_amc_mode: Check current amc mode status
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* @debug_dump: dump debug bus registers or enable debug bus
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* @state_update: Enable/override the solver based on rsc state
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* status (command/video)
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* @debug_show: Show current debug status.
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* @mode_ctrl: shows current mode status, mode0/1/2
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* @setup_counters: Enable/disable RSC profiling counters
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* @get_counters: Get current status of profiling counters
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*/
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struct sde_rsc_hw_ops {
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int (*init)(struct sde_rsc_priv *rsc);
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int (*timer_update)(struct sde_rsc_priv *rsc);
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int (*tcs_wait)(struct sde_rsc_priv *rsc);
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int (*hw_vsync)(struct sde_rsc_priv *rsc, enum rsc_vsync_req request,
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char *buffer, int buffer_size, u32 mode);
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int (*tcs_use_ok)(struct sde_rsc_priv *rsc);
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int (*bwi_status)(struct sde_rsc_priv *rsc, bool bw_indication);
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bool (*is_amc_mode)(struct sde_rsc_priv *rsc);
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void (*debug_dump)(struct sde_rsc_priv *rsc, u32 mux_sel);
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int (*state_update)(struct sde_rsc_priv *rsc, enum sde_rsc_state state);
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int (*debug_show)(struct seq_file *s, struct sde_rsc_priv *rsc);
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int (*mode_ctrl)(struct sde_rsc_priv *rsc, enum rsc_mode_req request,
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char *buffer, int buffer_size, u32 mode);
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int (*setup_counters)(struct sde_rsc_priv *rsc, bool enable);
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int (*get_counters)(struct sde_rsc_priv *rsc, u32 *counters);
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};
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/**
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* struct sde_rsc_timer_config: this is internal configuration between
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* rsc and rsc_hw API.
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*
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* @static_wakeup_time_ns: wrapper backoff time in nano seconds
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* @rsc_backoff_time_ns: rsc backoff time in nano seconds
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* @pdc_backoff_time_ns: pdc backoff time in nano seconds
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* @rsc_mode_threshold_time_ns: rsc mode threshold time in nano seconds
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* @rsc_time_slot_0_ns: mode-0 time slot threshold in nano seconds
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* @rsc_time_slot_1_ns: mode-1 time slot threshold in nano seconds
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* @rsc_time_slot_2_ns: mode-2 time slot threshold in nano seconds
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*
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* @min_threshold_time_ns: minimum time required to enter & exit mode0
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* @bwi_threshold_time_ns: worst case time to increase the BW vote
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*/
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struct sde_rsc_timer_config {
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u32 static_wakeup_time_ns;
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u32 rsc_backoff_time_ns;
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u32 pdc_backoff_time_ns;
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u32 rsc_mode_threshold_time_ns;
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u32 rsc_time_slot_0_ns;
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u32 rsc_time_slot_1_ns;
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u32 rsc_time_slot_2_ns;
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u32 min_threshold_time_ns;
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u32 bwi_threshold_time_ns;
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};
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/**
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* struct sde_rsc_bw_config: bandwidth configuration
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*
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* @ab_vote: Stored ab_vote for SDE_POWER_HANDLE_DBUS_ID_MAX
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* @ib_vote: Stored ib_vote for SDE_POWER_HANDLE_DBUS_ID_MAX
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* @new_ab_vote: ab_vote for incoming frame.
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* @new_ib_vote: ib_vote for incoming frame.
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*/
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struct sde_rsc_bw_config {
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u64 ab_vote[SDE_POWER_HANDLE_DBUS_ID_MAX];
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u64 ib_vote[SDE_POWER_HANDLE_DBUS_ID_MAX];
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u64 new_ab_vote[SDE_POWER_HANDLE_DBUS_ID_MAX];
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u64 new_ib_vote[SDE_POWER_HANDLE_DBUS_ID_MAX];
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};
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/**
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* struct sde_rsc_priv: sde resource state coordinator(rsc) private handle
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* @version: rsc sequence version
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* @hw_drv_ver: rscc hw version
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* @phandle: module power handle for clocks
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* @fs: "MDSS GDSC" handle
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* @sw_fs_enabled: track "MDSS GDSC" sw vote during probe
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*
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* @rpmh_dev: rpmh device node
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* @drv_io: sde drv io data mapping
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* @wrapper_io: wrapper io data mapping
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*
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* @client_list: current rsc client list handle
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* @event_list: current rsc event list handle
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* @client_lock: current rsc client synchronization lock
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*
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* timer_config: current rsc timer configuration
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* cmd_config: current panel config
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* current_state: current rsc state (video/command), solver
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* override/enabled.
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* vsync_source: Interface index to provide the vsync ticks
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* debug_mode: enables the logging for each register read/write
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* debugfs_root: debugfs file system root node
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*
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* hw_ops: sde rsc hardware operations
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* power_collapse: if all clients are in IDLE state then it enters in
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* mode2 state and enable the power collapse state
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* power_collapse_block:By default, rsc move to mode-2 if all clients are in
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* invalid state. It can be blocked by this boolean entry.
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* primary_client: A client which is allowed to make command state request
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* and ab/ib vote on display rsc
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* single_tcs_execution_time: worst case time to execute one tcs vote
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* (sleep/wake)
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* backoff_time_ns: time to only wake tcs in any mode
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* mode_threshold_time_ns: time to wake TCS in mode-0, must be greater than
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* backoff time
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* time_slot_0_ns: time for sleep & wake TCS in mode-1
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* master_drm: Primary client waits for vsync on this drm object based
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* on crtc id
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* rsc_vsync_wait: Refcount to indicate if we have to wait for the vsync.
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* rsc_vsync_waitq: Queue to wait for the vsync.
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* bw_config: check sde_rsc_bw_config structure description.
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* dev: rsc device node
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* resource_refcount: Track rsc resource refcount
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* profiling_supp: Indicates if HW has support for profiling counters
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* profiling_en: Flag for rsc lpm profiling counters, true=enabled
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* post_poms: bool if a panel mode change occurred
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*/
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struct sde_rsc_priv {
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u32 version;
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u32 hw_drv_ver;
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struct sde_power_handle phandle;
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struct regulator *fs;
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bool sw_fs_enabled;
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struct device *rpmh_dev;
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struct dss_io_data drv_io;
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struct dss_io_data wrapper_io;
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struct list_head client_list;
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struct list_head event_list;
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struct mutex client_lock;
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struct sde_rsc_timer_config timer_config;
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struct sde_rsc_cmd_config cmd_config;
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u32 current_state;
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u32 vsync_source;
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u32 debug_mode;
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struct dentry *debugfs_root;
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struct sde_rsc_hw_ops hw_ops;
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bool power_collapse;
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bool power_collapse_block;
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struct sde_rsc_client *primary_client;
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u32 single_tcs_execution_time;
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u32 backoff_time_ns;
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u32 mode_threshold_time_ns;
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u32 time_slot_0_ns;
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struct drm_device *master_drm;
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atomic_t rsc_vsync_wait;
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wait_queue_head_t rsc_vsync_waitq;
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struct sde_rsc_bw_config bw_config;
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struct device *dev;
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atomic_t resource_refcount;
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bool profiling_supp;
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bool profiling_en;
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bool post_poms;
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};
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/**
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* sde_rsc_hw_register() - register hardware API. It manages V1 and V2 support.
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: error code.
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*/
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int sde_rsc_hw_register(struct sde_rsc_priv *rsc);
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/**
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* sde_rsc_hw_register_v3() - register hardware API. It manages V3 support.
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*
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* @client: Client pointer provided by sde_rsc_client_create().
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*
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* Return: error code.
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*/
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int sde_rsc_hw_register_v3(struct sde_rsc_priv *rsc);
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#endif /* _SDE_RSC_PRIV_H_ */
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