b961099875
QPIC display is used to send frame data to panel over Qualcomm Parallel Interface Controller on MDM project. Old QPIC display driver is base on framebuffer framework, but now msm framebuffer driver is no longer used. So add supoport for QPIC display driver base on tiny DRM framework. Change-Id: I4f2434c9f9ad536e2ea56ed3daa6eb12ad56255b Signed-off-by: Lei Chen <chenlei@codeaurora.org>
138 lines
3.5 KiB
C
138 lines
3.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014-2015, 2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef __QPIC_DISPLAY_H__
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#define __QPIC_DISPLAY_H__
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#include <linux/clk.h>
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#include <linux/msm-sps.h>
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#include <linux/interrupt.h>
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#include <linux/interconnect.h>
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#include <linux/regulator/consumer.h>
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#include <linux/pinctrl/consumer.h>
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#include <drm/drm_drv.h>
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#include <drm/drm_connector.h>
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#include <drm/drm_simple_kms_helper.h>
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#define QPIC_REG_QPIC_LCDC_CTRL 0x22000
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#define QPIC_REG_LCDC_VERSION 0x22004
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#define QPIC_REG_QPIC_LCDC_IRQ_EN 0x22008
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#define QPIC_REG_QPIC_LCDC_IRQ_STTS 0x2200C
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#define QPIC_REG_QPIC_LCDC_IRQ_CLR 0x22010
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#define QPIC_REG_QPIC_LCDC_STTS 0x22014
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#define QPIC_REG_QPIC_LCDC_CMD_DATA_CYCLE_CNT 0x22018
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#define QPIC_REG_QPIC_LCDC_CFG0 0x22020
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#define QPIC_REG_QPIC_LCDC_CFG1 0x22024
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#define QPIC_REG_QPIC_LCDC_CFG2 0x22028
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#define QPIC_REG_QPIC_LCDC_RESET 0x2202C
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#define QPIC_REG_QPIC_LCDC_FIFO_SOF 0x22100
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#define QPIC_REG_LCD_DEVICE_CMD0 0x23000
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#define QPIC_REG_QPIC_LCDC_FIFO_DATA_PORT0 0x22140
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#define QPIC_REG_QPIC_LCDC_FIFO_EOF 0x22180
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#define QPIC_OUTP(qpic_display, off, data) \
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writel_relaxed((data), (qpic_display)->qpic_base + (off))
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#define QPIC_OUTPW(qpic_display, off, data) \
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writew_relaxed((data), (qpic_display)->qpic_base + (off))
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#define QPIC_INP(qpic_display, off) \
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readl_relaxed((qpic_display)->qpic_base + (off))
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#define QPIC_MAX_VSYNC_WAIT_TIME_IN_MS 500
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#define QPIC_MAX_CMD_BUF_SIZE_IN_BYTES 512
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#define QPIC_PINCTRL_STATE_DEFAULT "qpic_display_default"
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#define QPIC_PINCTRL_STATE_SLEEP "qpic_display_sleep"
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/* Structure that defines an SPS end point for a BAM pipe. */
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struct qpic_sps_endpt {
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struct sps_pipe *handle;
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struct sps_connect config;
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struct sps_register_event bam_event;
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struct completion completion;
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};
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struct qpic_panel_config {
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u32 xres;
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u32 yres;
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u32 bpp;
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u32 type;
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};
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struct qpic_pinctrl_res {
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struct pinctrl *pinctrl;
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struct pinctrl_state *gpio_state_active;
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struct pinctrl_state *gpio_state_suspend;
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};
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struct qpic_panel_io_desc {
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int rst_gpio;
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int cs_gpio;
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int ad8_gpio;
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int te_gpio;
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int bl_gpio;
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struct regulator *vdd_vreg;
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struct regulator *avdd_vreg;
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struct qpic_pinctrl_res pin_res;
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};
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struct bus_scaling_data {
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u64 ab;
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u64 ib;
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};
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struct msm_bus_path {
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unsigned int num_paths;
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struct bus_scaling_data *vec;
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};
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struct qpic_display_bus_scale_pdata {
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const char *name;
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unsigned int num_usecase;
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struct msm_bus_path *usecase;
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struct icc_path *data_bus_hdl;
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u32 curr_vote;
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};
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struct qpic_display_data {
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u32 rev;
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struct platform_device *pdev;
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struct drm_device drm_dev;
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struct drm_simple_display_pipe pipe;
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struct drm_connector conn;
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struct drm_display_mode drm_mode;
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bool pipe_enabled;
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size_t qpic_reg_size;
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u32 qpic_phys;
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char __iomem *qpic_base;
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u32 irq_id;
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bool irq_ena;
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u32 res_init;
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void *cmd_buf_virt;
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phys_addr_t cmd_buf_phys;
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struct qpic_sps_endpt qpic_endpt;
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u32 sps_init;
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u32 irq_requested;
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struct qpic_display_bus_scale_pdata *data_bus_pdata;
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struct completion fifo_eof_comp;
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bool is_qpic_on;
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struct clk *qpic_clk;
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struct clk *qpic_a_clk;
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int (*qpic_transfer)(struct qpic_display_data *qpic_display,
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u32 cmd, u8 *param, u32 len);
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bool is_panel_on;
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struct qpic_panel_config *panel_config;
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struct qpic_panel_io_desc panel_io;
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int (*panel_on)(struct qpic_display_data *qpic_display);
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void (*panel_off)(struct qpic_display_data *qpic_display);
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};
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int get_ili_qvga_panel_config(struct qpic_display_data *qpic_display);
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#endif
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