1f80025e62
Currently msi.c is doing sanity checks that make certain before an irq is destroyed it has no more users. By adding irq_has_action I can perform the test is a generic way, instead of relying on a msi specific data structure. By performing the core check in dynamic_irq_cleanup I ensure every user of dynamic irqs has a test present and we don't free resources that are in use. In msi.c this allows me to kill the attrib.state member of msi_desc and all of the assciated code to maintain it. To keep from freeing data structures when irq cleanup code is called to soon changing dyanamic_irq_cleanup is insufficient because there are msi specific data structures that are also not safe to free. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Tony Luck <tony.luck@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Greg KH <greg@kroah.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
78 lines
2.5 KiB
C
78 lines
2.5 KiB
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef MSI_H
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#define MSI_H
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#include <asm/msi.h>
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/*
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* MSI-X Address Register
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*/
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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#define PCI_MSIX_FLAGS_BITMASK (1 << 0)
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET 4
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#define PCI_MSIX_ENTRY_DATA_OFFSET 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET 12
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#define msi_control_reg(base) (base + PCI_MSI_FLAGS)
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#define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO)
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#define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI)
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#define msi_data_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
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#define msi_mask_bits_reg(base, is64bit) \
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( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
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#define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE
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#define multi_msi_capable(control) \
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(1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
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#define multi_msi_enable(control, num) \
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control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
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#define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT))
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#define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT))
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#define msi_enable(control, num) multi_msi_enable(control, num); \
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control |= PCI_MSI_FLAGS_ENABLE
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#define msix_table_offset_reg(base) (base + 0x04)
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#define msix_pba_offset_reg(base) (base + 0x08)
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#define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE
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#define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE
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#define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1)
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#define multi_msix_capable msix_table_size
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#define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK)
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#define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK)
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#define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK)
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struct msi_desc {
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struct {
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__u8 type : 5; /* {0: unused, 5h:MSI, 11h:MSI-X} */
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__u8 maskbit : 1; /* mask-pending bit supported ? */
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__u8 unused : 1;
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__u8 is_64 : 1; /* Address size: 0=32bit 1=64bit */
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__u8 pos; /* Location of the msi capability */
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__u16 entry_nr; /* specific enabled entry */
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unsigned default_irq; /* default pre-assigned irq */
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}msi_attrib;
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struct {
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__u16 head;
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__u16 tail;
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}link;
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void __iomem *mask_base;
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struct pci_dev *dev;
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#ifdef CONFIG_PM
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/* PM save area for MSIX address/data */
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struct msi_msg msg_save;
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#endif
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};
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#endif /* MSI_H */
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