7c241d37fe
This patch fixes PIO mode on the softmac bcm43xx driver. (A dscape patch will follow). It mainly fixes endianess issues. This patch is tested on PowerPC32 and i386. Signed-off-by: Michael Buesch <mb@bu3sch.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
227 lines
6.6 KiB
C
227 lines
6.6 KiB
C
#ifndef BCM43xx_DMA_H_
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#define BCM43xx_DMA_H_
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#include <linux/list.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/linkage.h>
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#include <asm/atomic.h>
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/* DMA-Interrupt reasons. */
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#define BCM43xx_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
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| (1 << 14) | (1 << 15))
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#define BCM43xx_DMAIRQ_NONFATALMASK (1 << 13)
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#define BCM43xx_DMAIRQ_RX_DONE (1 << 16)
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/* DMA controller register offsets. (relative to BCM43xx_DMA#_BASE) */
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#define BCM43xx_DMA_TX_CONTROL 0x00
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#define BCM43xx_DMA_TX_DESC_RING 0x04
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#define BCM43xx_DMA_TX_DESC_INDEX 0x08
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#define BCM43xx_DMA_TX_STATUS 0x0c
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#define BCM43xx_DMA_RX_CONTROL 0x10
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#define BCM43xx_DMA_RX_DESC_RING 0x14
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#define BCM43xx_DMA_RX_DESC_INDEX 0x18
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#define BCM43xx_DMA_RX_STATUS 0x1c
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/* DMA controller channel control word values. */
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#define BCM43xx_DMA_TXCTRL_ENABLE (1 << 0)
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#define BCM43xx_DMA_TXCTRL_SUSPEND (1 << 1)
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#define BCM43xx_DMA_TXCTRL_LOOPBACK (1 << 2)
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#define BCM43xx_DMA_TXCTRL_FLUSH (1 << 4)
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#define BCM43xx_DMA_RXCTRL_ENABLE (1 << 0)
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#define BCM43xx_DMA_RXCTRL_FRAMEOFF_MASK 0x000000fe
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#define BCM43xx_DMA_RXCTRL_FRAMEOFF_SHIFT 1
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#define BCM43xx_DMA_RXCTRL_PIO (1 << 8)
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/* DMA controller channel status word values. */
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#define BCM43xx_DMA_TXSTAT_DPTR_MASK 0x00000fff
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#define BCM43xx_DMA_TXSTAT_STAT_MASK 0x0000f000
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#define BCM43xx_DMA_TXSTAT_STAT_DISABLED 0x00000000
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#define BCM43xx_DMA_TXSTAT_STAT_ACTIVE 0x00001000
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#define BCM43xx_DMA_TXSTAT_STAT_IDLEWAIT 0x00002000
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#define BCM43xx_DMA_TXSTAT_STAT_STOPPED 0x00003000
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#define BCM43xx_DMA_TXSTAT_STAT_SUSP 0x00004000
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#define BCM43xx_DMA_TXSTAT_ERROR_MASK 0x000f0000
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#define BCM43xx_DMA_TXSTAT_FLUSHED (1 << 20)
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#define BCM43xx_DMA_RXSTAT_DPTR_MASK 0x00000fff
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#define BCM43xx_DMA_RXSTAT_STAT_MASK 0x0000f000
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#define BCM43xx_DMA_RXSTAT_STAT_DISABLED 0x00000000
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#define BCM43xx_DMA_RXSTAT_STAT_ACTIVE 0x00001000
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#define BCM43xx_DMA_RXSTAT_STAT_IDLEWAIT 0x00002000
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#define BCM43xx_DMA_RXSTAT_STAT_RESERVED 0x00003000
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#define BCM43xx_DMA_RXSTAT_STAT_ERRORS 0x00004000
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#define BCM43xx_DMA_RXSTAT_ERROR_MASK 0x000f0000
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/* DMA descriptor control field values. */
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#define BCM43xx_DMADTOR_BYTECNT_MASK 0x00001fff
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#define BCM43xx_DMADTOR_DTABLEEND (1 << 28) /* End of descriptor table */
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#define BCM43xx_DMADTOR_COMPIRQ (1 << 29) /* IRQ on completion request */
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#define BCM43xx_DMADTOR_FRAMEEND (1 << 30)
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#define BCM43xx_DMADTOR_FRAMESTART (1 << 31)
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/* Misc DMA constants */
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#define BCM43xx_DMA_RINGMEMSIZE PAGE_SIZE
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#define BCM43xx_DMA_BUSADDRMAX 0x3FFFFFFF
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#define BCM43xx_DMA_DMABUSADDROFFSET (1 << 30)
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#define BCM43xx_DMA1_RX_FRAMEOFFSET 30
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#define BCM43xx_DMA4_RX_FRAMEOFFSET 0
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/* DMA engine tuning knobs */
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#define BCM43xx_TXRING_SLOTS 512
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#define BCM43xx_RXRING_SLOTS 64
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#define BCM43xx_DMA1_RXBUFFERSIZE (2304 + 100)
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#define BCM43xx_DMA4_RXBUFFERSIZE 16
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/* Suspend the tx queue, if less than this percent slots are free. */
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#define BCM43xx_TXSUSPEND_PERCENT 20
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/* Resume the tx queue, if more than this percent slots are free. */
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#define BCM43xx_TXRESUME_PERCENT 50
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#ifdef CONFIG_BCM43XX_DMA
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struct sk_buff;
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struct bcm43xx_private;
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struct bcm43xx_xmitstatus;
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struct bcm43xx_dmadesc {
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__le32 _control;
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__le32 _address;
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} __attribute__((__packed__));
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/* Macros to access the bcm43xx_dmadesc struct */
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#define get_desc_ctl(desc) le32_to_cpu((desc)->_control)
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#define set_desc_ctl(desc, ctl) do { (desc)->_control = cpu_to_le32(ctl); } while (0)
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#define get_desc_addr(desc) le32_to_cpu((desc)->_address)
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#define set_desc_addr(desc, addr) do { (desc)->_address = cpu_to_le32(addr); } while (0)
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struct bcm43xx_dmadesc_meta {
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/* The kernel DMA-able buffer. */
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struct sk_buff *skb;
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/* DMA base bus-address of the descriptor buffer. */
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dma_addr_t dmaaddr;
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};
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struct bcm43xx_dmaring {
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struct bcm43xx_private *bcm;
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/* Kernel virtual base address of the ring memory. */
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struct bcm43xx_dmadesc *vbase;
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/* DMA memory offset */
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dma_addr_t memoffset;
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/* (Unadjusted) DMA base bus-address of the ring memory. */
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dma_addr_t dmabase;
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/* Meta data about all descriptors. */
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struct bcm43xx_dmadesc_meta *meta;
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/* Number of descriptor slots in the ring. */
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int nr_slots;
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/* Number of used descriptor slots. */
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int used_slots;
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/* Currently used slot in the ring. */
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int current_slot;
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/* Marks to suspend/resume the queue. */
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int suspend_mark;
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int resume_mark;
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/* Frameoffset in octets. */
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u32 frameoffset;
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/* Descriptor buffer size. */
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u16 rx_buffersize;
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/* The MMIO base register of the DMA controller, this
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* ring is posted to.
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*/
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u16 mmio_base;
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u8 tx:1, /* TRUE, if this is a TX ring. */
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suspended:1; /* TRUE, if transfers are suspended on this ring. */
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#ifdef CONFIG_BCM43XX_DEBUG
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/* Maximum number of used slots. */
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int max_used_slots;
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#endif /* CONFIG_BCM43XX_DEBUG*/
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};
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static inline
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u32 bcm43xx_dma_read(struct bcm43xx_dmaring *ring,
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u16 offset)
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{
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return bcm43xx_read32(ring->bcm, ring->mmio_base + offset);
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}
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static inline
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void bcm43xx_dma_write(struct bcm43xx_dmaring *ring,
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u16 offset, u32 value)
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{
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bcm43xx_write32(ring->bcm, ring->mmio_base + offset, value);
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}
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int bcm43xx_dma_init(struct bcm43xx_private *bcm);
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void bcm43xx_dma_free(struct bcm43xx_private *bcm);
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int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base);
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int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base);
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void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring);
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void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring);
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void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
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struct bcm43xx_xmitstatus *status);
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int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
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struct ieee80211_txb *txb);
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void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring);
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#else /* CONFIG_BCM43XX_DMA */
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static inline
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int bcm43xx_dma_init(struct bcm43xx_private *bcm)
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{
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return 0;
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}
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static inline
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void bcm43xx_dma_free(struct bcm43xx_private *bcm)
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{
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}
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static inline
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int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base)
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{
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return 0;
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}
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static inline
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int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
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u16 dmacontroller_mmio_base)
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{
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return 0;
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}
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static inline
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int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
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struct ieee80211_txb *txb)
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{
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return 0;
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}
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static inline
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void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
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struct bcm43xx_xmitstatus *status)
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{
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}
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static inline
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void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
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{
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}
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static inline
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void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
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{
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}
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static inline
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void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
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{
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}
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#endif /* CONFIG_BCM43XX_DMA */
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#endif /* BCM43xx_DMA_H_ */
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