e4ac58afdf
Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
197 lines
5.6 KiB
C
197 lines
5.6 KiB
C
/*
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* Copyright (C) 2003 PMC-Sierra Inc.
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* Author: Manish Lachwani (lachwani@pmc-sierra.com)
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*
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* Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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* Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
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*/
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/kernel_stat.h>
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#include <linux/module.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/timex.h>
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#include <linux/slab.h>
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#include <linux/random.h>
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#include <linux/bitops.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/system.h>
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#include <asm/titan_dep.h>
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/* Hypertransport specific */
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#define IRQ_ACK_BITS 0x00000000 /* Ack bits */
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#define HYPERTRANSPORT_INTA 0x78 /* INTA# */
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#define HYPERTRANSPORT_INTB 0x79 /* INTB# */
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#define HYPERTRANSPORT_INTC 0x7a /* INTC# */
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#define HYPERTRANSPORT_INTD 0x7b /* INTD# */
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extern void jaguar_mailbox_irq(struct pt_regs *);
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/*
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* Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
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* For interprocessor interrupts, the best thing to do is to use the INTMSG
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* register. We use the same external interrupt line, i.e. INTB3 and monitor
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* another status bit
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*/
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asmlinkage void ll_ht_smp_irq_handler(int irq, struct pt_regs *regs)
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{
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u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
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/* Ack all the bits that correspond to the interrupt sources */
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if (status != 0)
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OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
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status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
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if (status != 0)
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OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
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#ifdef CONFIG_HT_LEVEL_TRIGGER
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/*
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* Level Trigger Mode only. Send the HT EOI message back to the source.
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*/
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switch (status) {
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case 0x1000000:
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
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break;
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case 0x2000000:
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
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break;
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case 0x4000000:
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
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break;
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case 0x8000000:
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
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break;
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case 0x0000001:
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/* PLX */
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OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
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OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
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break;
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case 0xf000000:
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
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OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
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break;
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}
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#endif /* CONFIG_HT_LEVEL_TRIGGER */
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do_IRQ(irq, regs);
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}
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asmlinkage void do_extended_irq(struct pt_regs *regs)
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{
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unsigned int intcontrol = read_c0_intcontrol();
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unsigned int cause = read_c0_cause();
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unsigned int status = read_c0_status();
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unsigned int pending_sr, pending_ic;
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pending_sr = status & cause & 0xff00;
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pending_ic = (cause >> 8) & intcontrol & 0xff00;
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if (pending_ic & (1 << 13))
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do_IRQ(13, regs);
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}
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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unsigned int cause = read_c0_cause();
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unsigned int status = read_c0_status();
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unsigned int pending = cause & status;
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if (pending & STATUSF_IP7) {
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do_IRQ(7, regs);
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} else if (pending & STATUSF_IP2) {
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#ifdef CONFIG_HYPERTRANSPORT
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ll_ht_smp_irq_handler(2, regs);
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#else
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do_IRQ(2, regs);
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#endif
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} else if (pending & STATUSF_IP3) {
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do_IRQ(3, regs);
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} else if (pending & STATUSF_IP4) {
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do_IRQ(4, regs);
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} else if (pending & STATUSF_IP5) {
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#ifdef CONFIG_SMP
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titan_mailbox_irq(regs);
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#else
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do_IRQ(5, regs);
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#endif
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} else if (pending & STATUSF_IP6) {
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do_IRQ(4, regs);
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}
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}
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#ifdef CONFIG_KGDB
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extern void init_second_port(void);
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#endif
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/*
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* Initialize the next level interrupt handler
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*/
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void __init arch_init_irq(void)
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{
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clear_c0_status(ST0_IM);
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mips_cpu_irq_init(0);
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rm7k_cpu_irq_init(8);
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rm9k_cpu_irq_init(12);
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#ifdef CONFIG_KGDB
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/* At this point, initialize the second serial port */
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init_second_port();
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#endif
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#ifdef CONFIG_GDB_CONSOLE
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register_gdb_console();
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#endif
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}
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#ifdef CONFIG_KGDB
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/*
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* The 16550 DUART has two ports, but is allocated one IRQ
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* for the serial console. Hence, a generic framework for
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* serial IRQ routing in place. Currently, just calls the
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* do_IRQ fuction. But, going in the future, need to check
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* DUART registers for channel A and B, then decide the
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* appropriate action
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*/
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asmlinkage void yosemite_kgdb_irq(int irq, struct pt_regs *regs)
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{
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do_IRQ(irq, regs);
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}
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#endif
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