5daf9071b5
This patch merges align.c, the result isn't quite what was in ppc64 nor what was in ppc32 :) It should implement all the functionalities of both though. Kumar, since you played with that in the past, I suppose you have some test cases for verifying that it works properly before I dig out the 601 machine ? :) Since it's likely that I won't be able to test all scenario, code inspection is much welcome. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
531 lines
14 KiB
C
531 lines
14 KiB
C
/* align.c - handle alignment exceptions for the Power PC.
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*
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* Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
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* Copyright (c) 1998-1999 TiVo, Inc.
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* PowerPC 403GCX modifications.
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* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
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* PowerPC 403GCX/405GP modifications.
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* Copyright (c) 2001-2002 PPC64 team, IBM Corp
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* 64-bit and Power4 support
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* Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
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* <benh@kernel.crashing.org>
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* Merge ppc32 and ppc64 implementations
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/processor.h>
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#include <asm/uaccess.h>
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#include <asm/system.h>
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#include <asm/cache.h>
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#include <asm/cputable.h>
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struct aligninfo {
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unsigned char len;
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unsigned char flags;
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};
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#define IS_XFORM(inst) (((inst) >> 26) == 31)
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#define IS_DSFORM(inst) (((inst) >> 26) >= 56)
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#define INVALID { 0, 0 }
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#define LD 1 /* load */
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#define ST 2 /* store */
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#define SE 4 /* sign-extend value */
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#define F 8 /* to/from fp regs */
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#define U 0x10 /* update index register */
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#define M 0x20 /* multiple load/store */
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#define SW 0x40 /* byte swap int or ... */
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#define S 0x40 /* ... single-precision fp */
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#define SX 0x40 /* byte count in XER */
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#define HARD 0x80 /* string, stwcx. */
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#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
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#define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
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/*
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* The PowerPC stores certain bits of the instruction that caused the
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* alignment exception in the DSISR register. This array maps those
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* bits to information about the operand length and what the
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* instruction would do.
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*/
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static struct aligninfo aligninfo[128] = {
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{ 4, LD }, /* 00 0 0000: lwz / lwarx */
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INVALID, /* 00 0 0001 */
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{ 4, ST }, /* 00 0 0010: stw */
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INVALID, /* 00 0 0011 */
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{ 2, LD }, /* 00 0 0100: lhz */
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{ 2, LD+SE }, /* 00 0 0101: lha */
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{ 2, ST }, /* 00 0 0110: sth */
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{ 4, LD+M }, /* 00 0 0111: lmw */
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{ 4, LD+F+S }, /* 00 0 1000: lfs */
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{ 8, LD+F }, /* 00 0 1001: lfd */
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{ 4, ST+F+S }, /* 00 0 1010: stfs */
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{ 8, ST+F }, /* 00 0 1011: stfd */
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INVALID, /* 00 0 1100 */
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{ 8, LD }, /* 00 0 1101: ld/ldu/lwa */
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INVALID, /* 00 0 1110 */
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{ 8, ST }, /* 00 0 1111: std/stdu */
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{ 4, LD+U }, /* 00 1 0000: lwzu */
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INVALID, /* 00 1 0001 */
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{ 4, ST+U }, /* 00 1 0010: stwu */
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INVALID, /* 00 1 0011 */
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{ 2, LD+U }, /* 00 1 0100: lhzu */
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{ 2, LD+SE+U }, /* 00 1 0101: lhau */
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{ 2, ST+U }, /* 00 1 0110: sthu */
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{ 4, ST+M }, /* 00 1 0111: stmw */
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{ 4, LD+F+S+U }, /* 00 1 1000: lfsu */
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{ 8, LD+F+U }, /* 00 1 1001: lfdu */
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{ 4, ST+F+S+U }, /* 00 1 1010: stfsu */
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{ 8, ST+F+U }, /* 00 1 1011: stfdu */
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INVALID, /* 00 1 1100 */
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INVALID, /* 00 1 1101 */
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INVALID, /* 00 1 1110 */
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INVALID, /* 00 1 1111 */
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{ 8, LD }, /* 01 0 0000: ldx */
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INVALID, /* 01 0 0001 */
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{ 8, ST }, /* 01 0 0010: stdx */
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INVALID, /* 01 0 0011 */
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INVALID, /* 01 0 0100 */
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{ 4, LD+SE }, /* 01 0 0101: lwax */
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INVALID, /* 01 0 0110 */
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INVALID, /* 01 0 0111 */
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{ 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
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{ 4, LD+M+HARD }, /* 01 0 1001: lswi */
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{ 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
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{ 4, ST+M+HARD }, /* 01 0 1011: stswi */
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INVALID, /* 01 0 1100 */
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{ 8, LD+U }, /* 01 0 1101: ldu */
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INVALID, /* 01 0 1110 */
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{ 8, ST+U }, /* 01 0 1111: stdu */
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{ 8, LD+U }, /* 01 1 0000: ldux */
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INVALID, /* 01 1 0001 */
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{ 8, ST+U }, /* 01 1 0010: stdux */
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INVALID, /* 01 1 0011 */
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INVALID, /* 01 1 0100 */
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{ 4, LD+SE+U }, /* 01 1 0101: lwaux */
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INVALID, /* 01 1 0110 */
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INVALID, /* 01 1 0111 */
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INVALID, /* 01 1 1000 */
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INVALID, /* 01 1 1001 */
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INVALID, /* 01 1 1010 */
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INVALID, /* 01 1 1011 */
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INVALID, /* 01 1 1100 */
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INVALID, /* 01 1 1101 */
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INVALID, /* 01 1 1110 */
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INVALID, /* 01 1 1111 */
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INVALID, /* 10 0 0000 */
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INVALID, /* 10 0 0001 */
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INVALID, /* 10 0 0010: stwcx. */
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INVALID, /* 10 0 0011 */
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INVALID, /* 10 0 0100 */
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INVALID, /* 10 0 0101 */
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INVALID, /* 10 0 0110 */
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INVALID, /* 10 0 0111 */
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{ 4, LD+SW }, /* 10 0 1000: lwbrx */
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INVALID, /* 10 0 1001 */
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{ 4, ST+SW }, /* 10 0 1010: stwbrx */
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INVALID, /* 10 0 1011 */
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{ 2, LD+SW }, /* 10 0 1100: lhbrx */
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{ 4, LD+SE }, /* 10 0 1101 lwa */
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{ 2, ST+SW }, /* 10 0 1110: sthbrx */
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INVALID, /* 10 0 1111 */
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INVALID, /* 10 1 0000 */
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INVALID, /* 10 1 0001 */
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INVALID, /* 10 1 0010 */
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INVALID, /* 10 1 0011 */
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INVALID, /* 10 1 0100 */
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INVALID, /* 10 1 0101 */
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INVALID, /* 10 1 0110 */
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INVALID, /* 10 1 0111 */
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INVALID, /* 10 1 1000 */
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INVALID, /* 10 1 1001 */
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INVALID, /* 10 1 1010 */
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INVALID, /* 10 1 1011 */
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INVALID, /* 10 1 1100 */
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INVALID, /* 10 1 1101 */
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INVALID, /* 10 1 1110 */
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{ 0, ST+HARD }, /* 10 1 1111: dcbz */
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{ 4, LD }, /* 11 0 0000: lwzx */
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INVALID, /* 11 0 0001 */
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{ 4, ST }, /* 11 0 0010: stwx */
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INVALID, /* 11 0 0011 */
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{ 2, LD }, /* 11 0 0100: lhzx */
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{ 2, LD+SE }, /* 11 0 0101: lhax */
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{ 2, ST }, /* 11 0 0110: sthx */
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INVALID, /* 11 0 0111 */
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{ 4, LD+F+S }, /* 11 0 1000: lfsx */
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{ 8, LD+F }, /* 11 0 1001: lfdx */
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{ 4, ST+F+S }, /* 11 0 1010: stfsx */
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{ 8, ST+F }, /* 11 0 1011: stfdx */
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INVALID, /* 11 0 1100 */
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{ 8, LD+M }, /* 11 0 1101: lmd */
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INVALID, /* 11 0 1110 */
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{ 8, ST+M }, /* 11 0 1111: stmd */
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{ 4, LD+U }, /* 11 1 0000: lwzux */
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INVALID, /* 11 1 0001 */
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{ 4, ST+U }, /* 11 1 0010: stwux */
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INVALID, /* 11 1 0011 */
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{ 2, LD+U }, /* 11 1 0100: lhzux */
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{ 2, LD+SE+U }, /* 11 1 0101: lhaux */
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{ 2, ST+U }, /* 11 1 0110: sthux */
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INVALID, /* 11 1 0111 */
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{ 4, LD+F+S+U }, /* 11 1 1000: lfsux */
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{ 8, LD+F+U }, /* 11 1 1001: lfdux */
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{ 4, ST+F+S+U }, /* 11 1 1010: stfsux */
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{ 8, ST+F+U }, /* 11 1 1011: stfdux */
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INVALID, /* 11 1 1100 */
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INVALID, /* 11 1 1101 */
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INVALID, /* 11 1 1110 */
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INVALID, /* 11 1 1111 */
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};
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/*
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* Create a DSISR value from the instruction
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*/
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static inline unsigned make_dsisr(unsigned instr)
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{
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unsigned dsisr;
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/* bits 6:15 --> 22:31 */
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dsisr = (instr & 0x03ff0000) >> 16;
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if (IS_XFORM(instr)) {
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/* bits 29:30 --> 15:16 */
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dsisr |= (instr & 0x00000006) << 14;
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/* bit 25 --> 17 */
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dsisr |= (instr & 0x00000040) << 8;
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/* bits 21:24 --> 18:21 */
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dsisr |= (instr & 0x00000780) << 3;
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} else {
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/* bit 5 --> 17 */
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dsisr |= (instr & 0x04000000) >> 12;
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/* bits 1: 4 --> 18:21 */
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dsisr |= (instr & 0x78000000) >> 17;
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/* bits 30:31 --> 12:13 */
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if (IS_DSFORM(instr))
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dsisr |= (instr & 0x00000003) << 18;
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}
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return dsisr;
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}
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/*
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* The dcbz (data cache block zero) instruction
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* gives an alignment fault if used on non-cacheable
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* memory. We handle the fault mainly for the
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* case when we are running with the cache disabled
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* for debugging.
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*/
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static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
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{
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long __user *p;
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int i, size;
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#ifdef __powerpc64__
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size = ppc64_caches.dline_size;
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#else
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size = L1_CACHE_BYTES;
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#endif
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p = (long __user *) (regs->dar & -size);
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if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
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return -EFAULT;
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for (i = 0; i < size / sizeof(long); ++i)
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if (__put_user(0, p+i))
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return -EFAULT;
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return 1;
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}
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/*
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* Emulate load & store multiple instructions
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* On 64-bit machines, these instructions only affect/use the
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* bottom 4 bytes of each register, and the loads clear the
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* top 4 bytes of the affected register.
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*/
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#ifdef CONFIG_PPC64
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#define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
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#else
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#define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
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#endif
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static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
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unsigned int reg, unsigned int nb,
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unsigned int flags, unsigned int instr)
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{
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unsigned long *rptr;
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unsigned int nb0, i;
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/*
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* We do not try to emulate 8 bytes multiple as they aren't really
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* available in our operating environments and we don't try to
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* emulate multiples operations in kernel land as they should never
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* be used/generated there at least not on unaligned boundaries
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*/
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if (unlikely((nb > 4) || !user_mode(regs)))
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return 0;
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/* lmw, stmw, lswi/x, stswi/x */
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nb0 = 0;
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if (flags & HARD) {
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if (flags & SX) {
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nb = regs->xer & 127;
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if (nb == 0)
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return 1;
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} else {
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if (__get_user(instr,
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(unsigned int __user *)regs->nip))
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return -EFAULT;
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nb = (instr >> 11) & 0x1f;
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if (nb == 0)
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nb = 32;
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}
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if (nb + reg * 4 > 128) {
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nb0 = nb + reg * 4 - 128;
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nb = 128 - reg * 4;
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}
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} else {
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/* lwm, stmw */
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nb = (32 - reg) * 4;
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}
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if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
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return -EFAULT; /* bad address */
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rptr = ®s->gpr[reg];
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if (flags & LD) {
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/*
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* This zeroes the top 4 bytes of the affected registers
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* in 64-bit mode, and also zeroes out any remaining
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* bytes of the last register for lsw*.
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*/
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memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
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if (nb0 > 0)
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memset(®s->gpr[0], 0,
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((nb0 + 3) / 4) * sizeof(unsigned long));
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for (i = 0; i < nb; ++i)
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if (__get_user(REG_BYTE(rptr, i), addr + i))
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return -EFAULT;
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if (nb0 > 0) {
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rptr = ®s->gpr[0];
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addr += nb;
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for (i = 0; i < nb0; ++i)
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if (__get_user(REG_BYTE(rptr, i), addr + i))
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return -EFAULT;
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}
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} else {
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for (i = 0; i < nb; ++i)
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if (__put_user(REG_BYTE(rptr, i), addr + i))
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return -EFAULT;
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if (nb0 > 0) {
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rptr = ®s->gpr[0];
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addr += nb;
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for (i = 0; i < nb0; ++i)
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if (__put_user(REG_BYTE(rptr, i), addr + i))
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return -EFAULT;
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}
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}
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return 1;
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}
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/*
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* Called on alignment exception. Attempts to fixup
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*
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* Return 1 on success
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* Return 0 if unable to handle the interrupt
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* Return -EFAULT if data address is bad
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*/
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int fix_alignment(struct pt_regs *regs)
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{
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unsigned int instr, nb, flags;
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unsigned int reg, areg;
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unsigned int dsisr;
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unsigned char __user *addr;
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unsigned char __user *p;
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int ret, t;
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union {
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u64 ll;
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double dd;
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unsigned char v[8];
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struct {
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unsigned hi32;
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int low32;
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} x32;
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struct {
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unsigned char hi48[6];
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short low16;
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} x16;
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} data;
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/*
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* We require a complete register set, if not, then our assembly
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* is broken
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*/
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CHECK_FULL_REGS(regs);
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dsisr = regs->dsisr;
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/* Some processors don't provide us with a DSISR we can use here,
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* let's make one up from the instruction
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*/
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if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
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unsigned int real_instr;
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if (unlikely(__get_user(real_instr,
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(unsigned int __user *)regs->nip)))
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return -EFAULT;
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dsisr = make_dsisr(real_instr);
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}
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/* extract the operation and registers from the dsisr */
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reg = (dsisr >> 5) & 0x1f; /* source/dest register */
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areg = dsisr & 0x1f; /* register to update */
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instr = (dsisr >> 10) & 0x7f;
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instr |= (dsisr >> 13) & 0x60;
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/* Lookup the operation in our table */
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nb = aligninfo[instr].len;
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flags = aligninfo[instr].flags;
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/* DAR has the operand effective address */
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addr = (unsigned char __user *)regs->dar;
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/* A size of 0 indicates an instruction we don't support, with
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* the exception of DCBZ which is handled as a special case here
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*/
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if (instr == DCBZ)
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return emulate_dcbz(regs, addr);
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if (unlikely(nb == 0))
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return 0;
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/* Load/Store Multiple instructions are handled in their own
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* function
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*/
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if (flags & M)
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return emulate_multiple(regs, addr, reg, nb, flags, instr);
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/* Verify the address of the operand */
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if (unlikely(user_mode(regs) &&
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!access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
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addr, nb)))
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return -EFAULT;
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/* Force the fprs into the save area so we can reference them */
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if (flags & F) {
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/* userland only */
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if (unlikely(!user_mode(regs)))
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return 0;
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flush_fp_to_thread(current);
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}
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/* If we are loading, get the data from user space, else
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* get it from register values
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*/
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if (flags & LD) {
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data.ll = 0;
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ret = 0;
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p = addr;
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switch (nb) {
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case 8:
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ret |= __get_user(data.v[0], p++);
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ret |= __get_user(data.v[1], p++);
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ret |= __get_user(data.v[2], p++);
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ret |= __get_user(data.v[3], p++);
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case 4:
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ret |= __get_user(data.v[4], p++);
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ret |= __get_user(data.v[5], p++);
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case 2:
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ret |= __get_user(data.v[6], p++);
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ret |= __get_user(data.v[7], p++);
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if (unlikely(ret))
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return -EFAULT;
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}
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} else if (flags & F)
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data.dd = current->thread.fpr[reg];
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else
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data.ll = regs->gpr[reg];
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/* Perform other misc operations like sign extension, byteswap,
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* or floating point single precision conversion
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*/
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switch (flags & ~U) {
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case LD+SE: /* sign extend */
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if ( nb == 2 )
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data.ll = data.x16.low16;
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else /* nb must be 4 */
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data.ll = data.x32.low32;
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break;
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case LD+S: /* byte-swap */
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case ST+S:
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if (nb == 2) {
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SWAP(data.v[6], data.v[7]);
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} else {
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SWAP(data.v[4], data.v[7]);
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SWAP(data.v[5], data.v[6]);
|
|
}
|
|
break;
|
|
|
|
/* Single-precision FP load and store require conversions... */
|
|
case LD+F+S:
|
|
#ifdef CONFIG_PPC_FPU
|
|
preempt_disable();
|
|
enable_kernel_fp();
|
|
cvt_fd((float *)&data.v[4], &data.dd, ¤t->thread);
|
|
preempt_enable();
|
|
#else
|
|
return 0;
|
|
#endif
|
|
break;
|
|
case ST+F+S:
|
|
#ifdef CONFIG_PPC_FPU
|
|
preempt_disable();
|
|
enable_kernel_fp();
|
|
cvt_df(&data.dd, (float *)&data.v[4], ¤t->thread);
|
|
preempt_enable();
|
|
#else
|
|
return 0;
|
|
#endif
|
|
break;
|
|
}
|
|
|
|
/* Store result to memory or update registers */
|
|
if (flags & ST) {
|
|
ret = 0;
|
|
p = addr;
|
|
switch (nb) {
|
|
case 8:
|
|
ret |= __put_user(data.v[0], p++);
|
|
ret |= __put_user(data.v[1], p++);
|
|
ret |= __put_user(data.v[2], p++);
|
|
ret |= __put_user(data.v[3], p++);
|
|
case 4:
|
|
ret |= __put_user(data.v[4], p++);
|
|
ret |= __put_user(data.v[5], p++);
|
|
case 2:
|
|
ret |= __put_user(data.v[6], p++);
|
|
ret |= __put_user(data.v[7], p++);
|
|
}
|
|
if (unlikely(ret))
|
|
return -EFAULT;
|
|
} else if (flags & F)
|
|
current->thread.fpr[reg] = data.dd;
|
|
else
|
|
regs->gpr[reg] = data.ll;
|
|
|
|
/* Update RA as needed */
|
|
if (flags & U)
|
|
regs->gpr[areg] = regs->dar;
|
|
|
|
return 1;
|
|
}
|