343 lines
9.9 KiB
C
343 lines
9.9 KiB
C
/*
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* Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
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* Copyright (C) 2001 Ralf Baechle
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Routines for generic manipulation of the interrupts found on the MIPS
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* Malta board.
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* The interrupt controller is located in the South Bridge a PIIX4 device
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* with two internal 82C95 interrupt controllers.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/random.h>
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#include <asm/i8259.h>
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#include <asm/irq_cpu.h>
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#include <asm/io.h>
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#include <asm/mips-boards/malta.h>
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#include <asm/mips-boards/maltaint.h>
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#include <asm/mips-boards/piix4.h>
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#include <asm/gt64120.h>
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#include <asm/mips-boards/generic.h>
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#include <asm/mips-boards/msc01_pci.h>
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#include <asm/msc01_ic.h>
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extern void mips_timer_interrupt(void);
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static DEFINE_SPINLOCK(mips_irq_lock);
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static inline int mips_pcibios_iack(void)
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{
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int irq;
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u32 dummy;
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/*
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* Determine highest priority pending interrupt by performing
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* a PCI Interrupt Acknowledge cycle.
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*/
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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MSC_READ(MSC01_PCI_IACK, irq);
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irq &= 0xff;
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break;
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case MIPS_REVISION_CORID_QED_RM5261:
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case MIPS_REVISION_CORID_CORE_LV:
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case MIPS_REVISION_CORID_CORE_FPGA:
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case MIPS_REVISION_CORID_CORE_FPGAR2:
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irq = GT_READ(GT_PCI0_IACK_OFS);
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irq &= 0xff;
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break;
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case MIPS_REVISION_CORID_BONITO64:
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case MIPS_REVISION_CORID_CORE_20K:
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case MIPS_REVISION_CORID_CORE_EMUL_BON:
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/* The following will generate a PCI IACK cycle on the
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* Bonito controller. It's a little bit kludgy, but it
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* was the easiest way to implement it in hardware at
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* the given time.
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*/
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BONITO_PCIMAP_CFG = 0x20000;
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/* Flush Bonito register block */
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dummy = BONITO_PCIMAP_CFG;
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iob(); /* sync */
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irq = *(volatile u32 *)(_pcictrl_bonito_pcicfg);
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iob(); /* sync */
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irq &= 0xff;
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BONITO_PCIMAP_CFG = 0;
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break;
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default:
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printk("Unknown Core card, don't know the system controller.\n");
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return -1;
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}
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return irq;
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}
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static inline int get_int(void)
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{
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unsigned long flags;
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int irq;
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spin_lock_irqsave(&mips_irq_lock, flags);
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irq = mips_pcibios_iack();
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/*
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* The only way we can decide if an interrupt is spurious
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* is by checking the 8259 registers. This needs a spinlock
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* on an SMP system, so leave it up to the generic code...
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*/
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spin_unlock_irqrestore(&mips_irq_lock, flags);
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return irq;
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}
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static void malta_hw0_irqdispatch(struct pt_regs *regs)
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{
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int irq;
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irq = get_int();
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if (irq < 0) {
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return; /* interrupt has already been cleared */
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}
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do_IRQ(MALTA_INT_BASE+irq, regs);
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}
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void corehi_irqdispatch(struct pt_regs *regs)
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{
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unsigned int intrcause,datalo,datahi;
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unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
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printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
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printk("epc : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
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, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
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/* Read all the registers and then print them as there is a
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problem with interspersed printk's upsetting the Bonito controller.
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Do it for the others too.
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*/
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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ll_msc_irq(regs);
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break;
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case MIPS_REVISION_CORID_QED_RM5261:
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case MIPS_REVISION_CORID_CORE_LV:
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case MIPS_REVISION_CORID_CORE_FPGA:
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case MIPS_REVISION_CORID_CORE_FPGAR2:
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intrcause = GT_READ(GT_INTRCAUSE_OFS);
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datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
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datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
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printk("GT_INTRCAUSE = %08x\n", intrcause);
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printk("GT_CPUERR_ADDR = %02x%08x\n", datahi, datalo);
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break;
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case MIPS_REVISION_CORID_BONITO64:
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case MIPS_REVISION_CORID_CORE_20K:
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case MIPS_REVISION_CORID_CORE_EMUL_BON:
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pcibadaddr = BONITO_PCIBADADDR;
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pcimstat = BONITO_PCIMSTAT;
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intisr = BONITO_INTISR;
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inten = BONITO_INTEN;
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intpol = BONITO_INTPOL;
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intedge = BONITO_INTEDGE;
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intsteer = BONITO_INTSTEER;
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pcicmd = BONITO_PCICMD;
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printk("BONITO_INTISR = %08x\n", intisr);
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printk("BONITO_INTEN = %08x\n", inten);
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printk("BONITO_INTPOL = %08x\n", intpol);
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printk("BONITO_INTEDGE = %08x\n", intedge);
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printk("BONITO_INTSTEER = %08x\n", intsteer);
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printk("BONITO_PCICMD = %08x\n", pcicmd);
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printk("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
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printk("BONITO_PCIMSTAT = %08x\n", pcimstat);
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break;
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}
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/* We die here*/
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die("CoreHi interrupt", regs);
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}
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static inline int clz(unsigned long x)
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{
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__asm__ (
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" .set push \n"
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" .set mips32 \n"
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" clz %0, %1 \n"
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" .set pop \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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/*
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* Version of ffs that only looks at bits 12..15.
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*/
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static inline unsigned int irq_ffs(unsigned int pending)
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{
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#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
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return -clz(pending) + 31 - CAUSEB_IP;
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#else
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unsigned int a0 = 7;
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unsigned int t0;
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t0 = s0 & 0xf000;
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t0 = t0 < 1;
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t0 = t0 << 2;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0xc000;
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t0 = t0 < 1;
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t0 = t0 << 1;
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a0 = a0 - t0;
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s0 = s0 << t0;
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t0 = s0 & 0x8000;
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t0 = t0 < 1;
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//t0 = t0 << 2;
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a0 = a0 - t0;
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//s0 = s0 << t0;
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return a0;
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#endif
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}
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/*
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* IRQs on the Malta board look basically (barring software IRQs which we
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* don't use at all and all external interrupt sources are combined together
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* on hardware interrupt 0 (MIPS IRQ 2)) like:
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*
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* MIPS IRQ Source
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* -------- ------
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* 0 Software (ignored)
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* 1 Software (ignored)
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* 2 Combined hardware interrupt (hw0)
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* 3 Hardware (ignored)
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* 4 Hardware (ignored)
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* 5 Hardware (ignored)
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* 6 Hardware (ignored)
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* 7 R4k timer (what we use)
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*
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* We handle the IRQ according to _our_ priority which is:
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*
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* Highest ---- R4k Timer
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* Lowest ---- Combined hardware interrupt
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*
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* then we just return, if multiple IRQs are pending then we will just take
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* another exception, big deal.
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*/
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asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
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{
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unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
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int irq;
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irq = irq_ffs(pending);
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if (irq == MIPSCPU_INT_I8259A)
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malta_hw0_irqdispatch(regs);
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else if (irq > 0)
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do_IRQ(MIPSCPU_INT_BASE + irq, regs);
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else
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spurious_interrupt(regs);
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}
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static struct irqaction i8259irq = {
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.handler = no_action,
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.name = "XT-PIC cascade"
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};
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static struct irqaction corehi_irqaction = {
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.handler = no_action,
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.name = "CoreHi"
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};
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msc_irqmap_t __initdata msc_irqmap[] = {
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{MSC01C_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01C_INT_PCI, MSC01_IRQ_LEVEL, 0},
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};
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int __initdata msc_nr_irqs = sizeof(msc_irqmap)/sizeof(msc_irqmap_t);
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msc_irqmap_t __initdata msc_eicirqmap[] = {
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{MSC01E_INT_SW0, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SW1, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_I8259A, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_SMI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_COREHI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CORELO, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_TMR, MSC01_IRQ_EDGE, 0},
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{MSC01E_INT_PCI, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_PERFCTR, MSC01_IRQ_LEVEL, 0},
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{MSC01E_INT_CPUCTR, MSC01_IRQ_LEVEL, 0}
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};
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int __initdata msc_nr_eicirqs = sizeof(msc_eicirqmap)/sizeof(msc_irqmap_t);
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void __init arch_init_irq(void)
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{
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init_i8259_irqs();
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if (!cpu_has_veic)
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mips_cpu_irq_init (MIPSCPU_INT_BASE);
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switch(mips_revision_corid) {
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case MIPS_REVISION_CORID_CORE_MSC:
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case MIPS_REVISION_CORID_CORE_FPGA2:
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case MIPS_REVISION_CORID_CORE_FPGA3:
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case MIPS_REVISION_CORID_CORE_EMUL_MSC:
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if (cpu_has_veic)
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init_msc_irqs (MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
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else
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init_msc_irqs (MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
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}
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if (cpu_has_veic) {
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set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch);
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set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch);
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setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
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setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
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}
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else if (cpu_has_vint) {
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set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
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set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch);
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#ifdef CONFIG_MIPS_MT_SMTC
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setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq,
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(0x100 << MIPSCPU_INT_I8259A));
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setup_irq_smtc (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI,
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&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
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#else /* Not SMTC */
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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#endif /* CONFIG_MIPS_MT_SMTC */
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}
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else {
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPSCPU_INT_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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}
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}
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