a55f858852
* Add a few comments, and move the updation of max_power_level to a helper routine. This is also done by non-4K based chipsets, this will be fixed in a separate patch. * Remove two WARs which are required for old AR5416 chipsets, and are not needed for AR9287. * Fix indentation and make things readable. Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
303 lines
7.7 KiB
C
303 lines
7.7 KiB
C
/*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "hw.h"
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static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
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{
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if (fbin == AR5416_BCHAN_UNUSED)
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return fbin;
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return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
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}
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void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val)
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{
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REG_WRITE(ah, reg, val);
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if (ah->config.analog_shiftreg)
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udelay(100);
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}
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void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
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u32 shift, u32 val)
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{
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u32 regVal;
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regVal = REG_READ(ah, reg) & ~mask;
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regVal |= (val << shift) & mask;
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REG_WRITE(ah, reg, regVal);
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if (ah->config.analog_shiftreg)
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udelay(100);
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}
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int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
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int16_t targetLeft, int16_t targetRight)
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{
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int16_t rv;
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if (srcRight == srcLeft) {
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rv = targetLeft;
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} else {
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rv = (int16_t) (((target - srcLeft) * targetRight +
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(srcRight - target) * targetLeft) /
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(srcRight - srcLeft));
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}
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return rv;
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}
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bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
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u16 *indexL, u16 *indexR)
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{
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u16 i;
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if (target <= pList[0]) {
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*indexL = *indexR = 0;
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return true;
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}
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if (target >= pList[listSize - 1]) {
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*indexL = *indexR = (u16) (listSize - 1);
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return true;
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}
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for (i = 0; i < listSize - 1; i++) {
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if (pList[i] == target) {
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*indexL = *indexR = i;
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return true;
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}
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if (target < pList[i + 1]) {
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*indexL = i;
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*indexR = (u16) (i + 1);
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return false;
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}
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}
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return false;
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}
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bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data)
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{
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return common->bus_ops->eeprom_read(common, off, data);
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}
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void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
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u8 *pVpdList, u16 numIntercepts,
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u8 *pRetVpdList)
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{
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u16 i, k;
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u8 currPwr = pwrMin;
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u16 idxL = 0, idxR = 0;
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for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
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ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
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numIntercepts, &(idxL),
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&(idxR));
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if (idxR < 1)
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idxR = 1;
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if (idxL == numIntercepts - 1)
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idxL = (u16) (numIntercepts - 2);
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if (pPwrList[idxL] == pPwrList[idxR])
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k = pVpdList[idxL];
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else
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k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
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(pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
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(pPwrList[idxR] - pPwrList[idxL]));
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pRetVpdList[i] = (u8) k;
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currPwr += 2;
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}
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}
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void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct cal_target_power_leg *powInfo,
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u16 numChannels,
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struct cal_target_power_leg *pNewPower,
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u16 numRates, bool isExtTarget)
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{
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struct chan_centers centers;
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u16 clo, chi;
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int i;
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int matchIndex = -1, lowIndex = -1;
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u16 freq;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
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if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
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IS_CHAN_2GHZ(chan))) {
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matchIndex = 0;
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} else {
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for (i = 0; (i < numChannels) &&
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(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
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if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
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IS_CHAN_2GHZ(chan))) {
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matchIndex = i;
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break;
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} else if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
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IS_CHAN_2GHZ(chan)) && i > 0 &&
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freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
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IS_CHAN_2GHZ(chan))) {
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lowIndex = i - 1;
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break;
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}
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}
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if ((matchIndex == -1) && (lowIndex == -1))
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matchIndex = i - 1;
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}
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if (matchIndex != -1) {
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*pNewPower = powInfo[matchIndex];
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} else {
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clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
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IS_CHAN_2GHZ(chan));
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chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
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IS_CHAN_2GHZ(chan));
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for (i = 0; i < numRates; i++) {
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pNewPower->tPow2x[i] =
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(u8)ath9k_hw_interpolate(freq, clo, chi,
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powInfo[lowIndex].tPow2x[i],
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powInfo[lowIndex + 1].tPow2x[i]);
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}
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}
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}
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void ath9k_hw_get_target_powers(struct ath_hw *ah,
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struct ath9k_channel *chan,
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struct cal_target_power_ht *powInfo,
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u16 numChannels,
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struct cal_target_power_ht *pNewPower,
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u16 numRates, bool isHt40Target)
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{
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struct chan_centers centers;
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u16 clo, chi;
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int i;
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int matchIndex = -1, lowIndex = -1;
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u16 freq;
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ath9k_hw_get_channel_centers(ah, chan, ¢ers);
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freq = isHt40Target ? centers.synth_center : centers.ctl_center;
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if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
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matchIndex = 0;
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} else {
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for (i = 0; (i < numChannels) &&
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(powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
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if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
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IS_CHAN_2GHZ(chan))) {
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matchIndex = i;
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break;
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} else
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if (freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
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IS_CHAN_2GHZ(chan)) && i > 0 &&
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freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
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IS_CHAN_2GHZ(chan))) {
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lowIndex = i - 1;
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break;
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}
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}
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if ((matchIndex == -1) && (lowIndex == -1))
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matchIndex = i - 1;
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}
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if (matchIndex != -1) {
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*pNewPower = powInfo[matchIndex];
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} else {
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clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
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IS_CHAN_2GHZ(chan));
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chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
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IS_CHAN_2GHZ(chan));
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for (i = 0; i < numRates; i++) {
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pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
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clo, chi,
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powInfo[lowIndex].tPow2x[i],
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powInfo[lowIndex + 1].tPow2x[i]);
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}
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}
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}
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u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
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bool is2GHz, int num_band_edges)
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{
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u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
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int i;
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for (i = 0; (i < num_band_edges) &&
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(pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
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if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
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twiceMaxEdgePower = pRdEdgesPower[i].tPower;
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break;
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} else if ((i > 0) &&
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(freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
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is2GHz))) {
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if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
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is2GHz) < freq &&
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pRdEdgesPower[i - 1].flag) {
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twiceMaxEdgePower =
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pRdEdgesPower[i - 1].tPower;
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}
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break;
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}
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}
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return twiceMaxEdgePower;
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}
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void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah)
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{
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
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switch (ar5416_get_ntxchains(ah->txchainmask)) {
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case 1:
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break;
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case 2:
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regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
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break;
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case 3:
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regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
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break;
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default:
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ath_print(common, ATH_DBG_EEPROM,
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"Invalid chainmask configuration\n");
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break;
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}
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}
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int ath9k_hw_eeprom_init(struct ath_hw *ah)
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{
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int status;
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if (AR_SREV_9300_20_OR_LATER(ah))
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ah->eep_ops = &eep_ar9300_ops;
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else if (AR_SREV_9287(ah)) {
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ah->eep_ops = &eep_ar9287_ops;
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} else if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) {
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ah->eep_ops = &eep_4k_ops;
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} else {
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ah->eep_ops = &eep_def_ops;
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}
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if (!ah->eep_ops->fill_eeprom(ah))
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return -EIO;
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status = ah->eep_ops->check_eeprom(ah);
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return status;
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}
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