bbacee13f4
AR5008+ and AR9003 currently use two separate implementations of the ath9k_hw_loadnf function. There are three main differences: - PHY registers for AR9003 are different - AR9003 always uses 3 chains, earlier versions are more selective - The AR9003 variant contains a fix for NF load timeouts This patch merges the two implementations into one, storing the register array in the ath_hw struct. The fix for NF load timeouts is not just relevant for AR9003, but also important for earlier hardware, so it's better to just keep one common implementation. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
291 lines
7.6 KiB
C
291 lines
7.6 KiB
C
/*
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* Copyright (c) 2010 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef ATH9K_HW_OPS_H
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#define ATH9K_HW_OPS_H
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#include "hw.h"
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/* Hardware core and driver accessible callbacks */
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static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
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int restore,
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int power_off)
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{
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ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
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}
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static inline void ath9k_hw_rxena(struct ath_hw *ah)
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{
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ath9k_hw_ops(ah)->rx_enable(ah);
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}
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static inline void ath9k_hw_set_desc_link(struct ath_hw *ah, void *ds,
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u32 link)
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{
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ath9k_hw_ops(ah)->set_desc_link(ds, link);
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}
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static inline void ath9k_hw_get_desc_link(struct ath_hw *ah, void *ds,
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u32 **link)
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{
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ath9k_hw_ops(ah)->get_desc_link(ds, link);
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}
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static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
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struct ath9k_channel *chan,
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u8 rxchainmask,
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bool longcal)
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{
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return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
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}
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static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
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{
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return ath9k_hw_ops(ah)->get_isr(ah, masked);
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}
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static inline void ath9k_hw_filltxdesc(struct ath_hw *ah, void *ds, u32 seglen,
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bool is_firstseg, bool is_lastseg,
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const void *ds0, dma_addr_t buf_addr,
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unsigned int qcu)
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{
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ath9k_hw_ops(ah)->fill_txdesc(ah, ds, seglen, is_firstseg, is_lastseg,
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ds0, buf_addr, qcu);
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}
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static inline int ath9k_hw_txprocdesc(struct ath_hw *ah, void *ds,
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struct ath_tx_status *ts)
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{
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return ath9k_hw_ops(ah)->proc_txdesc(ah, ds, ts);
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}
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static inline void ath9k_hw_set11n_txdesc(struct ath_hw *ah, void *ds,
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u32 pktLen, enum ath9k_pkt_type type,
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u32 txPower, u32 keyIx,
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enum ath9k_key_type keyType,
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u32 flags)
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{
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ath9k_hw_ops(ah)->set11n_txdesc(ah, ds, pktLen, type, txPower, keyIx,
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keyType, flags);
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}
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static inline void ath9k_hw_set11n_ratescenario(struct ath_hw *ah, void *ds,
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void *lastds,
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u32 durUpdateEn, u32 rtsctsRate,
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u32 rtsctsDuration,
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struct ath9k_11n_rate_series series[],
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u32 nseries, u32 flags)
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{
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ath9k_hw_ops(ah)->set11n_ratescenario(ah, ds, lastds, durUpdateEn,
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rtsctsRate, rtsctsDuration, series,
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nseries, flags);
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}
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static inline void ath9k_hw_set11n_aggr_first(struct ath_hw *ah, void *ds,
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u32 aggrLen)
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{
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ath9k_hw_ops(ah)->set11n_aggr_first(ah, ds, aggrLen);
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}
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static inline void ath9k_hw_set11n_aggr_middle(struct ath_hw *ah, void *ds,
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u32 numDelims)
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{
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ath9k_hw_ops(ah)->set11n_aggr_middle(ah, ds, numDelims);
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}
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static inline void ath9k_hw_set11n_aggr_last(struct ath_hw *ah, void *ds)
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{
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ath9k_hw_ops(ah)->set11n_aggr_last(ah, ds);
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}
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static inline void ath9k_hw_clr11n_aggr(struct ath_hw *ah, void *ds)
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{
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ath9k_hw_ops(ah)->clr11n_aggr(ah, ds);
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}
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static inline void ath9k_hw_set11n_burstduration(struct ath_hw *ah, void *ds,
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u32 burstDuration)
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{
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ath9k_hw_ops(ah)->set11n_burstduration(ah, ds, burstDuration);
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}
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static inline void ath9k_hw_set11n_virtualmorefrag(struct ath_hw *ah, void *ds,
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u32 vmf)
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{
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ath9k_hw_ops(ah)->set11n_virtualmorefrag(ah, ds, vmf);
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}
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static inline void ath9k_hw_procmibevent(struct ath_hw *ah)
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{
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ath9k_hw_ops(ah)->ani_proc_mib_event(ah);
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}
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static inline void ath9k_hw_ani_monitor(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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ath9k_hw_ops(ah)->ani_monitor(ah, chan);
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}
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/* Private hardware call ops */
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/* PHY ops */
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static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
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}
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static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
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}
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static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
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return 0;
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return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
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}
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static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
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return;
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ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
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}
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static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
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struct ath9k_channel *chan,
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u16 modesIndex)
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{
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if (!ath9k_hw_private_ops(ah)->set_rf_regs)
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return true;
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return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
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}
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static inline void ath9k_hw_init_bb(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
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}
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static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
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}
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static inline int ath9k_hw_process_ini(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
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}
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static inline void ath9k_olc_init(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->olc_init)
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return;
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return ath9k_hw_private_ops(ah)->olc_init(ah);
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}
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static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
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}
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static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
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{
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return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
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}
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static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
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}
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static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
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{
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return ath9k_hw_private_ops(ah)->rfbus_req(ah);
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}
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static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
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{
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return ath9k_hw_private_ops(ah)->rfbus_done(ah);
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}
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static inline void ath9k_enable_rfkill(struct ath_hw *ah)
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{
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return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
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}
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static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
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{
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if (!ath9k_hw_private_ops(ah)->restore_chainmask)
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return;
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return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
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}
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static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
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{
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return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
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}
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static inline bool ath9k_hw_ani_control(struct ath_hw *ah,
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enum ath9k_ani_cmd cmd, int param)
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{
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return ath9k_hw_private_ops(ah)->ani_control(ah, cmd, param);
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}
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static inline void ath9k_hw_do_getnf(struct ath_hw *ah,
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int16_t nfarray[NUM_NF_READINGS])
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{
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ath9k_hw_private_ops(ah)->do_getnf(ah, nfarray);
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}
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static inline bool ath9k_hw_init_cal(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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return ath9k_hw_private_ops(ah)->init_cal(ah, chan);
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}
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static inline void ath9k_hw_setup_calibration(struct ath_hw *ah,
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struct ath9k_cal_list *currCal)
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{
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ath9k_hw_private_ops(ah)->setup_calibration(ah, currCal);
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}
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static inline bool ath9k_hw_iscal_supported(struct ath_hw *ah,
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enum ath9k_cal_types calType)
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{
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return ath9k_hw_private_ops(ah)->iscal_supported(ah, calType);
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}
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static inline void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning)
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{
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ath9k_hw_private_ops(ah)->ani_reset(ah, is_scanning);
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}
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#endif /* ATH9K_HW_OPS_H */
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