[ Upstream commit 264b82fdb4989cf6a44a2bcd0c6ea05e8026b2ac ]
The 4-to-5 level mode switch trampoline disables long mode and paging in
order to be able to flick the LA57 bit. According to section 3.4.1.1 of
the x86 architecture manual [0], 64-bit GPRs might not retain the upper
32 bits of their contents across such a mode switch.
Given that RBP, RBX and RSI are live at this point, preserve them on the
stack, along with the return address that might be above 4G as well.
[0] Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic Architecture
"Because the upper 32 bits of 64-bit general-purpose registers are
undefined in 32-bit modes, the upper 32 bits of any general-purpose
register are not preserved when switching from 64-bit mode to a 32-bit
mode (to protected mode or compatibility mode). Software must not
depend on these bits to maintain a value after a 64-bit to 32-bit
mode switch."
Fixes:
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.. | ||
compressed | ||
tools | ||
.gitignore | ||
a20.c | ||
apm.c | ||
bioscall.S | ||
bitops.h | ||
boot.h | ||
cmdline.c | ||
code16gcc.h | ||
copy.S | ||
cpu.c | ||
cpucheck.c | ||
cpuflags.c | ||
cpuflags.h | ||
ctype.h | ||
early_serial_console.c | ||
edd.c | ||
genimage.sh | ||
header.S | ||
install.sh | ||
main.c | ||
Makefile | ||
memory.c | ||
mkcpustr.c | ||
mtools.conf.in | ||
pm.c | ||
pmjump.S | ||
printf.c | ||
regs.c | ||
setup.ld | ||
string.c | ||
string.h | ||
tty.c | ||
version.c | ||
vesa.h | ||
video-bios.c | ||
video-mode.c | ||
video-vesa.c | ||
video-vga.c | ||
video.c | ||
video.h |