356 lines
8.4 KiB
C
356 lines
8.4 KiB
C
/* linux/arch/arm/plat-s3c24xx/cpu.c
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*
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* Copyright (c) 2004-2005 Simtec Electronics
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* http://www.simtec.co.uk/products/SWLINUX/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C24XX CPU Support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/cacheflush.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/system-reset.h>
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#include <mach/regs-gpio.h>
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#include <asm/plat-s3c/regs-serial.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/s3c2400.h>
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#include <asm/plat-s3c24xx/s3c2410.h>
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#include <asm/plat-s3c24xx/s3c2412.h>
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#include "s3c244x.h"
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#include <asm/plat-s3c24xx/s3c2440.h>
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#include <asm/plat-s3c24xx/s3c2442.h>
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#include <asm/plat-s3c24xx/s3c2443.h>
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struct cpu_table {
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unsigned long idcode;
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unsigned long idmask;
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void (*map_io)(struct map_desc *mach_desc, int size);
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void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
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void (*init_clocks)(int xtal);
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int (*init)(void);
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const char *name;
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};
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/* table of supported CPUs */
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static const char name_s3c2400[] = "S3C2400";
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static const char name_s3c2410[] = "S3C2410";
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static const char name_s3c2412[] = "S3C2412";
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static const char name_s3c2440[] = "S3C2440";
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static const char name_s3c2442[] = "S3C2442";
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static const char name_s3c2443[] = "S3C2443";
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static const char name_s3c2410a[] = "S3C2410A";
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static const char name_s3c2440a[] = "S3C2440A";
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static struct cpu_table cpu_ids[] __initdata = {
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{
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.idcode = 0x32410000,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410
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},
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{
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.idcode = 0x32410002,
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.idmask = 0xffffffff,
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.map_io = s3c2410_map_io,
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.init_clocks = s3c2410_init_clocks,
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.init_uarts = s3c2410_init_uarts,
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.init = s3c2410_init,
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.name = name_s3c2410a
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},
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{
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.idcode = 0x32440000,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440
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},
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{
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.idcode = 0x32440001,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2440_init,
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.name = name_s3c2440a
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},
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{
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.idcode = 0x32440aaa,
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.idmask = 0xffffffff,
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.map_io = s3c244x_map_io,
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.init_clocks = s3c244x_init_clocks,
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.init_uarts = s3c244x_init_uarts,
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.init = s3c2442_init,
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.name = name_s3c2442
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},
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{
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.idcode = 0x32412001,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{ /* a newer version of the s3c2412 */
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.idcode = 0x32412003,
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.idmask = 0xffffffff,
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.map_io = s3c2412_map_io,
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.init_clocks = s3c2412_init_clocks,
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.init_uarts = s3c2412_init_uarts,
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.init = s3c2412_init,
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.name = name_s3c2412,
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},
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{
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.idcode = 0x32443001,
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.idmask = 0xffffffff,
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.map_io = s3c2443_map_io,
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.init_clocks = s3c2443_init_clocks,
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.init_uarts = s3c2443_init_uarts,
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.init = s3c2443_init,
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.name = name_s3c2443,
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},
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{
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.idcode = 0x0, /* S3C2400 doesn't have an idcode */
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.idmask = 0xffffffff,
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.map_io = s3c2400_map_io,
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.init_clocks = s3c2400_init_clocks,
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.init_uarts = s3c2400_init_uarts,
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.init = s3c2400_init,
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.name = name_s3c2400
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},
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};
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/* minimal IO mapping */
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static struct map_desc s3c_iodesc[] __initdata = {
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IODESC_ENT(GPIO),
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IODESC_ENT(IRQ),
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IODESC_ENT(MEMCTRL),
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IODESC_ENT(UART)
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};
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static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode)
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{
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struct cpu_table *tab;
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int count;
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tab = cpu_ids;
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for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
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if ((idcode & tab->idmask) == tab->idcode)
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return tab;
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}
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return NULL;
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}
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/* cpu information */
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static struct cpu_table *cpu;
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static unsigned long s3c24xx_read_idcode_v5(void)
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{
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#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
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return __raw_readl(S3C2412_GSTATUS1);
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#else
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return 1UL; /* don't look like an 2400 */
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#endif
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}
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static unsigned long s3c24xx_read_idcode_v4(void)
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{
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#ifndef CONFIG_CPU_S3C2400
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return __raw_readl(S3C2410_GSTATUS1);
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#else
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return 0UL;
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#endif
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}
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/* Hook for arm_pm_restart to ensure we execute the reset code
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* with the caches enabled. It seems at least the S3C2440 has a problem
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* resetting if there is bus activity interrupted by the reset.
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*/
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static void s3c24xx_pm_restart(char mode)
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{
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if (mode != 's') {
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unsigned long flags;
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local_irq_save(flags);
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__cpuc_flush_kern_all();
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__cpuc_flush_user_all();
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arch_reset(mode);
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local_irq_restore(flags);
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}
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/* fallback, or unhandled */
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arm_machine_restart(mode);
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}
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void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
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{
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unsigned long idcode = 0x0;
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/* initialise the io descriptors we need for initialisation */
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iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
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if (cpu_architecture() >= CPU_ARCH_ARMv5) {
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idcode = s3c24xx_read_idcode_v5();
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} else {
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idcode = s3c24xx_read_idcode_v4();
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}
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cpu = s3c_lookup_cpu(idcode);
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if (cpu == NULL) {
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printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
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panic("Unknown S3C24XX CPU");
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}
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printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
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if (cpu->map_io == NULL || cpu->init == NULL) {
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printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
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panic("Unsupported S3C24XX CPU");
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}
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arm_pm_restart = s3c24xx_pm_restart;
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(cpu->map_io)(mach_desc, size);
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}
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/* s3c24xx_init_clocks
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*
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* Initialise the clock subsystem and associated information from the
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* given master crystal value.
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*
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* xtal = 0 -> use default PLL crystal value (normally 12MHz)
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* != 0 -> PLL crystal value in Hz
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*/
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void __init s3c24xx_init_clocks(int xtal)
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{
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if (xtal == 0)
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xtal = 12*1000*1000;
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if (cpu == NULL)
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panic("s3c24xx_init_clocks: no cpu setup?\n");
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if (cpu->init_clocks == NULL)
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panic("s3c24xx_init_clocks: cpu has no clock init\n");
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else
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(cpu->init_clocks)(xtal);
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}
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/* uart management */
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static int nr_uarts __initdata = 0;
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static struct s3c2410_uartcfg uart_cfgs[3];
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/* s3c24xx_init_uartdevs
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*
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* copy the specified platform data and configuration into our central
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* set of devices, before the data is thrown away after the init process.
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*
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* This also fills in the array passed to the serial driver for the
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* early initialisation of the console.
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*/
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void __init s3c24xx_init_uartdevs(char *name,
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struct s3c24xx_uart_resources *res,
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struct s3c2410_uartcfg *cfg, int no)
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{
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struct platform_device *platdev;
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struct s3c2410_uartcfg *cfgptr = uart_cfgs;
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struct s3c24xx_uart_resources *resp;
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int uart;
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memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
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for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
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platdev = s3c24xx_uart_src[cfgptr->hwport];
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resp = res + cfgptr->hwport;
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s3c24xx_uart_devs[uart] = platdev;
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platdev->name = name;
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platdev->resource = resp->resources;
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platdev->num_resources = resp->nr_resources;
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platdev->dev.platform_data = cfgptr;
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}
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nr_uarts = no;
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}
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void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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{
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if (cpu == NULL)
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return;
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if (cpu->init_uarts == NULL) {
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printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
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} else
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(cpu->init_uarts)(cfg, no);
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}
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static int __init s3c_arch_init(void)
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{
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int ret;
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// do the correct init for cpu
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if (cpu == NULL)
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panic("s3c_arch_init: NULL cpu\n");
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ret = (cpu->init)();
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if (ret != 0)
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return ret;
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ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
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return ret;
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}
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arch_initcall(s3c_arch_init);
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