a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
/* swift.h: Specific definitions for the _broken_ Swift SRMMU
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* MMU module.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_SWIFT_H
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#define _SPARC_SWIFT_H
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/* Swift is so brain damaged, here is the mmu control register. */
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#define SWIFT_ST 0x00800000 /* SW tablewalk enable */
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#define SWIFT_WP 0x00400000 /* Watchpoint enable */
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/* Branch folding (buggy, disable on production systems!) */
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#define SWIFT_BF 0x00200000
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#define SWIFT_PMC 0x00180000 /* Page mode control */
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#define SWIFT_PE 0x00040000 /* Parity enable */
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#define SWIFT_PC 0x00020000 /* Parity control */
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#define SWIFT_AP 0x00010000 /* Graphics page mode control (TCX/SX) */
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#define SWIFT_AC 0x00008000 /* Alternate Cacheability (see viking.h) */
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#define SWIFT_BM 0x00004000 /* Boot mode */
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#define SWIFT_RC 0x00003c00 /* DRAM refresh control */
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#define SWIFT_IE 0x00000200 /* Instruction cache enable */
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#define SWIFT_DE 0x00000100 /* Data cache enable */
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#define SWIFT_SA 0x00000080 /* Store Allocate */
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#define SWIFT_NF 0x00000002 /* No fault mode */
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#define SWIFT_EN 0x00000001 /* MMU enable */
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/* Bits [13:5] select one of 512 instruction cache tags */
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static inline void swift_inv_insn_tag(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_TXTC_TAG)
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: "memory");
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}
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/* Bits [12:4] select one of 512 data cache tags */
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static inline void swift_inv_data_tag(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_DATAC_TAG)
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: "memory");
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}
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static inline void swift_flush_dcache(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x2000; addr += 0x10)
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swift_inv_data_tag(addr);
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}
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static inline void swift_flush_icache(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x4000; addr += 0x20)
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swift_inv_insn_tag(addr);
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}
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static inline void swift_idflash_clear(void)
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{
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unsigned long addr;
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for (addr = 0; addr < 0x2000; addr += 0x10) {
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swift_inv_insn_tag(addr<<1);
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swift_inv_data_tag(addr);
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}
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}
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/* Swift is so broken, it isn't even safe to use the following. */
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static inline void swift_flush_page(unsigned long page)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (page), "i" (ASI_M_FLUSH_PAGE)
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: "memory");
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}
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static inline void swift_flush_segment(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_FLUSH_SEG)
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: "memory");
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}
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static inline void swift_flush_region(unsigned long addr)
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t"
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: /* no outputs */
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: "r" (addr), "i" (ASI_M_FLUSH_REGION)
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: "memory");
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}
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static inline void swift_flush_context(void)
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{
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__asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
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: /* no outputs */
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: "i" (ASI_M_FLUSH_CTX)
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: "memory");
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}
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#endif /* !(_SPARC_SWIFT_H) */
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