0c3bd83b09
After the common MIPS CPU interrupt controller (for irq0-7) was introduced the Lasat boards didn't get their interrupts right, so nothing worked. The old routines need to be offset by the new 8 hardware interrupts common to all MIPS CPU's. Signed-off-by: Thomas Horsten <thomas@horsten.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
14 lines
455 B
C
14 lines
455 B
C
#include <asm/lasat/lasat.h>
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/* Lasat 100 boards serial configuration */
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#define LASAT_BASE_BAUD_100 (7372800 / 16)
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#define LASAT_UART_REGS_BASE_100 0x1c8b0000
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#define LASAT_UART_REGS_SHIFT_100 2
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#define LASATINT_UART_100 16
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/* * LASAT 200 boards serial configuration */
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#define LASAT_BASE_BAUD_200 (100000000 / 16 / 12)
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#define LASAT_UART_REGS_BASE_200 (Vrc5074_PHYS_BASE + 0x0300)
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#define LASAT_UART_REGS_SHIFT_200 3
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#define LASATINT_UART_200 21
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