162 lines
4.7 KiB
C
162 lines
4.7 KiB
C
/*
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* Cobalt Qube/Raq PCI support
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <asm/gt64120.h>
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#include <asm/cobalt/cobalt.h>
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extern int cobalt_board_id;
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static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
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{
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if (dev->devfn == PCI_DEVFN(0, 0) &&
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(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
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dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
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printk(KERN_INFO "Galileo: fixed bridge class\n");
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
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qube_raq_galileo_early_fixup);
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static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
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{
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unsigned short cfgword;
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unsigned char lt;
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/* Enable Bus Mastering and fast back to back. */
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pci_read_config_word(dev, PCI_COMMAND, &cfgword);
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cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
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pci_write_config_word(dev, PCI_COMMAND, cfgword);
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/* Enable both ide interfaces. ROM only enables primary one. */
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pci_write_config_byte(dev, 0x40, 0xb);
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/* Set latency timer to reasonable value. */
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, <);
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if (lt < 64)
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
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qube_raq_via_bmIDE_fixup);
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static void qube_raq_galileo_fixup(struct pci_dev *dev)
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{
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unsigned short galileo_id;
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if (dev->devfn != PCI_DEVFN(0, 0))
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return;
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/* Fix PCI latency-timer and cache-line-size values in Galileo
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* host bridge.
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*/
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 7);
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/*
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* The code described by the comment below has been removed
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* as it causes bus mastering by the Ethernet controllers
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* to break under any kind of network load. We always set
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* the retry timeouts to their maximum.
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*
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* --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
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*
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* On all machines prior to Q2, we had the STOP line disconnected
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* from Galileo to VIA on PCI. The new Galileo does not function
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* correctly unless we have it connected.
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*
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* Therefore we must set the disconnect/retry cycle values to
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* something sensible when using the new Galileo.
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*/
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pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id);
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galileo_id &= 0xff; /* mask off class info */
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printk(KERN_INFO "Galileo: revision %u\n", galileo_id);
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#if 0
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if (galileo_id >= 0x10) {
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/* New Galileo, assumes PCI stop line to VIA is connected. */
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GALILEO_OUTL(0x4020, GT_PCI0_TOR_OFS);
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} else if (galileo_id == 0x1 || galileo_id == 0x2)
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#endif
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{
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signed int timeo;
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/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
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timeo = GALILEO_INL(GT_PCI0_TOR_OFS);
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/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
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GALILEO_OUTL(
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(0xff << 16) | /* retry count */
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(0xff << 8) | /* timeout 1 */
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0xff, /* timeout 0 */
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GT_PCI0_TOR_OFS);
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/* enable PCI retry exceeded interrupt */
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GALILEO_OUTL(GALILEO_INTR_RETRY_CTR | GALILEO_INL(GT_INTRMASK_OFS), GT_INTRMASK_OFS);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
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qube_raq_galileo_fixup);
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static char irq_tab_qube1[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_ETH1] = 0
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};
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static char irq_tab_cobalt[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
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};
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static char irq_tab_raq2[] __initdata = {
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[COBALT_PCICONF_CPU] = 0,
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[COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ,
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[COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ,
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[COBALT_PCICONF_VIA] = 0,
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[COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ,
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[COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ
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};
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int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (cobalt_board_id < COBALT_BRD_ID_QUBE2)
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return irq_tab_qube1[slot];
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if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
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return irq_tab_raq2[slot];
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return irq_tab_cobalt[slot];
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}
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/* Do platform specific device initialization at pci_enable_device() time */
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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return 0;
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}
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