6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
/*
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* Author: Armin Kuster <akuster@mvista.com>
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*
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* 2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_IBMNP405H_H__
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#define __ASM_IBMNP405H_H__
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/* ibm405.h at bottom of this file */
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#define PPC405_PCI_CONFIG_ADDR 0xeec00000
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#define PPC405_PCI_CONFIG_DATA 0xeec00004
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#define PPC405_PCI_PHY_MEM_BASE 0x80000000 /* hose_a->pci_mem_offset */
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/* setbat */
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#define PPC405_PCI_MEM_BASE PPC405_PCI_PHY_MEM_BASE /* setbat */
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#define PPC405_PCI_PHY_IO_BASE 0xe8000000 /* setbat */
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#define PPC405_PCI_IO_BASE PPC405_PCI_PHY_IO_BASE /* setbat */
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#define PPC405_PCI_LOWER_MEM 0x00000000 /* hose_a->mem_space.start */
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#define PPC405_PCI_UPPER_MEM 0xBfffffff /* hose_a->mem_space.end */
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#define PPC405_PCI_LOWER_IO 0x00000000 /* hose_a->io_space.start */
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#define PPC405_PCI_UPPER_IO 0x0000ffff /* hose_a->io_space.end */
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#define PPC405_ISA_IO_BASE PPC405_PCI_IO_BASE
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#define PPC4xx_PCI_IO_ADDR ((uint)PPC405_PCI_PHY_IO_BASE)
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#define PPC4xx_PCI_IO_SIZE ((uint)64*1024)
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#define PPC4xx_PCI_CFG_ADDR ((uint)PPC405_PCI_CONFIG_ADDR)
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#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024)
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#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000)
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#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024)
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#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000)
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#define PPC4xx_ONB_IO_SIZE ((uint)4*1024)
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/* serial port defines */
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#define RS_TABLE_SIZE 4
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#define UART0_INT 0
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#define UART1_INT 1
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#define PCIL0_BASE 0xEF400000
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#define UART0_IO_BASE 0xEF600300
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#define UART1_IO_BASE 0xEF600400
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#define OPB0_BASE 0xEF600600
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#define EMAC0_BASE 0xEF600800
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#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
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#define STD_UART_OP(num) \
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{ 0, BASE_BAUD, 0, UART##num##_INT, \
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(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST), \
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iomem_base:(u8 *) UART##num##_IO_BASE, \
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io_type: SERIAL_IO_MEM},
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#if defined(CONFIG_UART0_TTYS0)
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#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(0) \
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STD_UART_OP(1)
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#endif
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#if defined(CONFIG_UART0_TTYS1)
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#define SERIAL_DEBUG_IO_BASE UART0_IO_BASE
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#define SERIAL_PORT_DFNS \
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STD_UART_OP(1) \
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STD_UART_OP(0)
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#endif
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/* DCR defines */
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/* ------------------------------------------------------------------------- */
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#define DCRN_CHCR_BASE 0x0F1
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#define DCRN_CHPSR_BASE 0x0B4
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#define DCRN_CPMSR_BASE 0x0BA
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#define DCRN_CPMFR_BASE 0x0B9
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#define DCRN_CPMER_BASE 0x0B8
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/* CPM Clocking & Power Mangement defines */
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#define IBM_CPM_PCI 0x40000000 /* PCI */
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#define IBM_CPM_EMAC2 0x20000000 /* EMAC 2 MII */
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#define IBM_CPM_EMAC3 0x04000000 /* EMAC 3 MII */
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#define IBM_CPM_EMAC0 0x00800000 /* EMAC 0 MII */
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#define IBM_CPM_EMAC1 0x00100000 /* EMAC 1 MII */
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#define IBM_CPM_EMMII 0 /* Shift value for MII */
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#define IBM_CPM_EMRX 1 /* Shift value for recv */
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#define IBM_CPM_EMTX 2 /* Shift value for MAC */
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#define IBM_CPM_UIC1 0x00020000 /* Universal Interrupt Controller */
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#define IBM_CPM_UIC0 0x00010000 /* Universal Interrupt Controller */
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#define IBM_CPM_CPU 0x00008000 /* processor core */
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#define IBM_CPM_EBC 0x00004000 /* ROM/SRAM peripheral controller */
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#define IBM_CPM_SDRAM0 0x00002000 /* SDRAM memory controller */
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#define IBM_CPM_GPIO0 0x00001000 /* General Purpose IO (??) */
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#define IBM_CPM_HDLC 0x00000800 /* HDCL */
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#define IBM_CPM_TMRCLK 0x00000400 /* CPU timers */
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#define IBM_CPM_PLB 0x00000100 /* PLB bus arbiter */
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#define IBM_CPM_OPB 0x00000080 /* PLB to OPB bridge */
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#define IBM_CPM_DMA 0x00000040 /* DMA controller */
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#define IBM_CPM_IIC0 0x00000010 /* IIC interface */
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#define IBM_CPM_UART0 0x00000002 /* serial port 0 */
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#define IBM_CPM_UART1 0x00000001 /* serial port 1 */
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/* this is the default setting for devices put to sleep when booting */
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#define DFLT_IBM4xx_PM ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
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| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
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| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA \
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| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
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| IBM_CPM_EMAC3 | IBM_CPM_PCI)
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#define DCRN_DMA0_BASE 0x100
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#define DCRN_DMA1_BASE 0x108
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#define DCRN_DMA2_BASE 0x110
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#define DCRN_DMA3_BASE 0x118
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#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
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#define DCRN_DMASR_BASE 0x120
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#define DCRN_EBC_BASE 0x012
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#define DCRN_DCP0_BASE 0x014
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#define DCRN_MAL_BASE 0x180
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#define DCRN_OCM0_BASE 0x018
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#define DCRN_PLB0_BASE 0x084
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#define DCRN_PLLMR_BASE 0x0B0
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#define DCRN_POB0_BASE 0x0A0
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#define DCRN_SDRAM0_BASE 0x010
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#define DCRN_UIC0_BASE 0x0C0
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#define DCRN_UIC1_BASE 0x0D0
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#define DCRN_CPC0_EPRCSR 0x0F3
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#define UIC0_UIC1NC 0x00000002
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#define CHR1_CETE 0x00000004 /* CPU external timer enable */
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#define UIC0 DCRN_UIC0_BASE
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#define UIC1 DCRN_UIC1_BASE
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#undef NR_UICS
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#define NR_UICS 2
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/* EMAC DCRN's FIXME: armin */
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#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
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#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
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#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
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#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
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#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
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#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
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#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
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#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
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#include <asm/ibm405.h>
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#endif /* __ASM_IBMNP405H_H__ */
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#endif /* __KERNEL__ */
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