256f7276af
Although reporting of benign GART TLB errors is disabled in __mcheck_cpu_apply_quirks, those are still being logged, and, as a result, trip up amd64_edac. Pull up reporting check so that machines with loaded edac module bail out early and don't spit fragments into dmesg. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
446 lines
10 KiB
C
446 lines
10 KiB
C
#include <linux/module.h>
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#include "edac_mce_amd.h"
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static bool report_gart_errors;
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static void (*nb_bus_decoder)(int node_id, struct err_regs *regs);
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void amd_report_gart_errors(bool v)
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{
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report_gart_errors = v;
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}
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EXPORT_SYMBOL_GPL(amd_report_gart_errors);
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void amd_register_ecc_decoder(void (*f)(int, struct err_regs *))
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{
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nb_bus_decoder = f;
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}
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EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);
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void amd_unregister_ecc_decoder(void (*f)(int, struct err_regs *))
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{
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if (nb_bus_decoder) {
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WARN_ON(nb_bus_decoder != f);
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nb_bus_decoder = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);
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/*
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* string representation for the different MCA reported error types, see F3x48
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* or MSR0000_0411.
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*/
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const char *tt_msgs[] = { /* transaction type */
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"instruction",
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"data",
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"generic",
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"reserved"
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};
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EXPORT_SYMBOL_GPL(tt_msgs);
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const char *ll_msgs[] = { /* cache level */
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"L0",
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"L1",
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"L2",
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"L3/generic"
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};
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EXPORT_SYMBOL_GPL(ll_msgs);
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const char *rrrr_msgs[] = {
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"generic",
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"generic read",
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"generic write",
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"data read",
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"data write",
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"inst fetch",
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"prefetch",
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"evict",
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"snoop",
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"reserved RRRR= 9",
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"reserved RRRR= 10",
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"reserved RRRR= 11",
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"reserved RRRR= 12",
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"reserved RRRR= 13",
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"reserved RRRR= 14",
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"reserved RRRR= 15"
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};
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EXPORT_SYMBOL_GPL(rrrr_msgs);
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const char *pp_msgs[] = { /* participating processor */
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"local node originated (SRC)",
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"local node responded to request (RES)",
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"local node observed as 3rd party (OBS)",
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"generic"
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};
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EXPORT_SYMBOL_GPL(pp_msgs);
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const char *to_msgs[] = {
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"no timeout",
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"timed out"
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};
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EXPORT_SYMBOL_GPL(to_msgs);
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const char *ii_msgs[] = { /* memory or i/o */
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"mem access",
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"reserved",
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"i/o access",
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"generic"
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};
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EXPORT_SYMBOL_GPL(ii_msgs);
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/*
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* Map the 4 or 5 (family-specific) bits of Extended Error code to the
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* string table.
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*/
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const char *ext_msgs[] = {
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"K8 ECC error", /* 0_0000b */
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"CRC error on link", /* 0_0001b */
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"Sync error packets on link", /* 0_0010b */
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"Master Abort during link operation", /* 0_0011b */
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"Target Abort during link operation", /* 0_0100b */
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"Invalid GART PTE entry during table walk", /* 0_0101b */
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"Unsupported atomic RMW command received", /* 0_0110b */
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"WDT error: NB transaction timeout", /* 0_0111b */
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"ECC/ChipKill ECC error", /* 0_1000b */
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"SVM DEV Error", /* 0_1001b */
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"Link Data error", /* 0_1010b */
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"Link/L3/Probe Filter Protocol error", /* 0_1011b */
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"NB Internal Arrays Parity error", /* 0_1100b */
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"DRAM Address/Control Parity error", /* 0_1101b */
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"Link Transmission error", /* 0_1110b */
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"GART/DEV Table Walk Data error" /* 0_1111b */
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"Res 0x100 error", /* 1_0000b */
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"Res 0x101 error", /* 1_0001b */
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"Res 0x102 error", /* 1_0010b */
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"Res 0x103 error", /* 1_0011b */
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"Res 0x104 error", /* 1_0100b */
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"Res 0x105 error", /* 1_0101b */
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"Res 0x106 error", /* 1_0110b */
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"Res 0x107 error", /* 1_0111b */
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"Res 0x108 error", /* 1_1000b */
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"Res 0x109 error", /* 1_1001b */
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"Res 0x10A error", /* 1_1010b */
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"Res 0x10B error", /* 1_1011b */
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"ECC error in L3 Cache Data", /* 1_1100b */
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"L3 Cache Tag error", /* 1_1101b */
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"L3 Cache LRU Parity error", /* 1_1110b */
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"Probe Filter error" /* 1_1111b */
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};
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EXPORT_SYMBOL_GPL(ext_msgs);
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static void amd_decode_dc_mce(u64 mc0_status)
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{
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u32 ec = mc0_status & 0xffff;
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u32 xec = (mc0_status >> 16) & 0xf;
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pr_emerg(" Data Cache Error");
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if (xec == 1 && TLB_ERROR(ec))
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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else if (xec == 0) {
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if (mc0_status & (1ULL << 40))
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pr_cont(" during Data Scrub.\n");
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else if (TLB_ERROR(ec))
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pr_cont(": %s TLB parity error.\n", LL_MSG(ec));
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else if (MEM_ERROR(ec)) {
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u8 ll = ec & 0x3;
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u8 tt = (ec >> 2) & 0x3;
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u8 rrrr = (ec >> 4) & 0xf;
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/* see F10h BKDG (31116), Table 92. */
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if (ll == 0x1) {
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if (tt != 0x1)
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goto wrong_dc_mce;
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pr_cont(": Data/Tag %s error.\n", RRRR_MSG(ec));
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} else if (ll == 0x2 && rrrr == 0x3)
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pr_cont(" during L1 linefill from L2.\n");
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else
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goto wrong_dc_mce;
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} else if (BUS_ERROR(ec) && boot_cpu_data.x86 == 0xf)
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pr_cont(" during system linefill.\n");
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else
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goto wrong_dc_mce;
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} else
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goto wrong_dc_mce;
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return;
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wrong_dc_mce:
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pr_warning("Corrupted DC MCE info?\n");
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}
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static void amd_decode_ic_mce(u64 mc1_status)
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{
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u32 ec = mc1_status & 0xffff;
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u32 xec = (mc1_status >> 16) & 0xf;
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pr_emerg(" Instruction Cache Error");
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if (xec == 1 && TLB_ERROR(ec))
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pr_cont(": %s TLB multimatch.\n", LL_MSG(ec));
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else if (xec == 0) {
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if (TLB_ERROR(ec))
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pr_cont(": %s TLB Parity error.\n", LL_MSG(ec));
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else if (BUS_ERROR(ec)) {
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if (boot_cpu_data.x86 == 0xf &&
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(mc1_status & (1ULL << 58)))
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pr_cont(" during system linefill.\n");
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else
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pr_cont(" during attempted NB data read.\n");
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} else if (MEM_ERROR(ec)) {
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u8 ll = ec & 0x3;
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u8 rrrr = (ec >> 4) & 0xf;
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if (ll == 0x2)
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pr_cont(" during a linefill from L2.\n");
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else if (ll == 0x1) {
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switch (rrrr) {
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case 0x5:
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pr_cont(": Parity error during "
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"data load.\n");
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break;
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case 0x7:
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pr_cont(": Copyback Parity/Victim"
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" error.\n");
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break;
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case 0x8:
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pr_cont(": Tag Snoop error.\n");
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break;
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default:
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goto wrong_ic_mce;
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break;
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}
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}
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} else
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goto wrong_ic_mce;
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} else
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goto wrong_ic_mce;
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return;
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wrong_ic_mce:
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pr_warning("Corrupted IC MCE info?\n");
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}
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static void amd_decode_bu_mce(u64 mc2_status)
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{
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u32 ec = mc2_status & 0xffff;
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u32 xec = (mc2_status >> 16) & 0xf;
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pr_emerg(" Bus Unit Error");
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if (xec == 0x1)
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pr_cont(" in the write data buffers.\n");
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else if (xec == 0x3)
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pr_cont(" in the victim data buffers.\n");
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else if (xec == 0x2 && MEM_ERROR(ec))
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pr_cont(": %s error in the L2 cache tags.\n", RRRR_MSG(ec));
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else if (xec == 0x0) {
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if (TLB_ERROR(ec))
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pr_cont(": %s error in a Page Descriptor Cache or "
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"Guest TLB.\n", TT_MSG(ec));
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else if (BUS_ERROR(ec))
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pr_cont(": %s/ECC error in data read from NB: %s.\n",
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RRRR_MSG(ec), PP_MSG(ec));
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else if (MEM_ERROR(ec)) {
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u8 rrrr = (ec >> 4) & 0xf;
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if (rrrr >= 0x7)
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pr_cont(": %s error during data copyback.\n",
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RRRR_MSG(ec));
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else if (rrrr <= 0x1)
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pr_cont(": %s parity/ECC error during data "
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"access from L2.\n", RRRR_MSG(ec));
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else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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} else
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goto wrong_bu_mce;
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return;
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wrong_bu_mce:
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pr_warning("Corrupted BU MCE info?\n");
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}
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static void amd_decode_ls_mce(u64 mc3_status)
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{
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u32 ec = mc3_status & 0xffff;
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u32 xec = (mc3_status >> 16) & 0xf;
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pr_emerg(" Load Store Error");
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if (xec == 0x0) {
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u8 rrrr = (ec >> 4) & 0xf;
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if (!BUS_ERROR(ec) || (rrrr != 0x3 && rrrr != 0x4))
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goto wrong_ls_mce;
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pr_cont(" during %s.\n", RRRR_MSG(ec));
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}
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return;
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wrong_ls_mce:
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pr_warning("Corrupted LS MCE info?\n");
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}
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void amd_decode_nb_mce(int node_id, struct err_regs *regs, int handle_errors)
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{
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u32 ec = ERROR_CODE(regs->nbsl);
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u32 xec = EXT_ERROR_CODE(regs->nbsl);
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if (!handle_errors)
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return;
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/*
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* GART TLB error reporting is disabled by default. Bail out early.
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*/
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if (TLB_ERROR(ec) && !report_gart_errors)
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return;
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pr_emerg(" Northbridge Error, node %d", node_id);
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/*
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* F10h, revD can disable ErrCpu[3:0] so check that first and also the
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* value encoding has changed so interpret those differently
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*/
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if ((boot_cpu_data.x86 == 0x10) &&
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(boot_cpu_data.x86_model > 7)) {
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if (regs->nbsh & K8_NBSH_ERR_CPU_VAL)
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pr_cont(", core: %u\n", (u8)(regs->nbsh & 0xf));
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} else {
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pr_cont(", core: %d\n", fls((regs->nbsh & 0xf) - 1));
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}
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pr_emerg("%s.\n", EXT_ERR_MSG(xec));
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if (BUS_ERROR(ec) && nb_bus_decoder)
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nb_bus_decoder(node_id, regs);
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}
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EXPORT_SYMBOL_GPL(amd_decode_nb_mce);
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static void amd_decode_fr_mce(u64 mc5_status)
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{
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/* we have only one error signature so match all fields at once. */
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if ((mc5_status & 0xffff) == 0x0f0f)
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pr_emerg(" FR Error: CPU Watchdog timer expire.\n");
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else
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pr_warning("Corrupted FR MCE info?\n");
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}
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static inline void amd_decode_err_code(unsigned int ec)
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{
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if (TLB_ERROR(ec)) {
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pr_emerg(" Transaction: %s, Cache Level %s\n",
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TT_MSG(ec), LL_MSG(ec));
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} else if (MEM_ERROR(ec)) {
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pr_emerg(" Transaction: %s, Type: %s, Cache Level: %s",
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RRRR_MSG(ec), TT_MSG(ec), LL_MSG(ec));
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} else if (BUS_ERROR(ec)) {
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pr_emerg(" Transaction type: %s(%s), %s, Cache Level: %s, "
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"Participating Processor: %s\n",
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RRRR_MSG(ec), II_MSG(ec), TO_MSG(ec), LL_MSG(ec),
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PP_MSG(ec));
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} else
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pr_warning("Huh? Unknown MCE error 0x%x\n", ec);
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}
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static int amd_decode_mce(struct notifier_block *nb, unsigned long val,
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void *data)
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{
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struct mce *m = (struct mce *)data;
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struct err_regs regs;
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int node, ecc;
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pr_emerg("MC%d_STATUS: ", m->bank);
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pr_cont("%sorrected error, report: %s, MiscV: %svalid, "
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"CPU context corrupt: %s",
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((m->status & MCI_STATUS_UC) ? "Unc" : "C"),
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((m->status & MCI_STATUS_EN) ? "yes" : "no"),
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((m->status & MCI_STATUS_MISCV) ? "" : "in"),
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((m->status & MCI_STATUS_PCC) ? "yes" : "no"));
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/* do the two bits[14:13] together */
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ecc = m->status & (3ULL << 45);
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if (ecc)
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pr_cont(", %sECC Error", ((ecc == 2) ? "C" : "U"));
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pr_cont("\n");
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switch (m->bank) {
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case 0:
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amd_decode_dc_mce(m->status);
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break;
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case 1:
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amd_decode_ic_mce(m->status);
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break;
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case 2:
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amd_decode_bu_mce(m->status);
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break;
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case 3:
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amd_decode_ls_mce(m->status);
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break;
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case 4:
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regs.nbsl = (u32) m->status;
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbeal = (u32) m->addr;
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regs.nbeah = (u32)(m->addr >> 32);
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node = amd_get_nb_id(m->extcpu);
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amd_decode_nb_mce(node, ®s, 1);
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break;
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case 5:
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amd_decode_fr_mce(m->status);
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break;
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default:
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break;
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}
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amd_decode_err_code(m->status & 0xffff);
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return NOTIFY_STOP;
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}
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static struct notifier_block amd_mce_dec_nb = {
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.notifier_call = amd_decode_mce,
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};
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static int __init mce_amd_init(void)
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{
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/*
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* We can decode MCEs for Opteron and later CPUs:
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*/
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if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
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(boot_cpu_data.x86 >= 0xf))
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atomic_notifier_chain_register(&x86_mce_decoder_chain, &amd_mce_dec_nb);
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return 0;
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}
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early_initcall(mce_amd_init);
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#ifdef MODULE
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static void __exit mce_amd_exit(void)
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{
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atomic_notifier_chain_unregister(&x86_mce_decoder_chain, &amd_mce_dec_nb);
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}
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MODULE_DESCRIPTION("AMD MCE decoder");
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MODULE_ALIAS("edac-mce-amd");
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MODULE_LICENSE("GPL");
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module_exit(mce_amd_exit);
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#endif
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