4e73238d16
The interrupt enable bit for the performance counters is in the Control
Register $24, not in the counter register.
loongson2_perfcount_handler(), we need to use
Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn>
Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/1198/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
174 lines
4.7 KiB
C
174 lines
4.7 KiB
C
/*
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* Loongson2 performance counter driver for oprofile
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*
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* Copyright (C) 2009 Lemote Inc.
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* Author: Yanhua <yanh@lemote.com>
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* Author: Wu Zhangjin <wuzhangjin@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/oprofile.h>
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#include <linux/interrupt.h>
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#include <loongson.h> /* LOONGSON2_PERFCNT_IRQ */
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#include "op_impl.h"
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/*
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* a patch should be sent to oprofile with the loongson-specific support.
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* otherwise, the oprofile tool will not recognize this and complain about
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* "cpu_type 'unset' is not valid".
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*/
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#define LOONGSON2_CPU_TYPE "mips/loongson2"
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#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5)
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#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9)
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#define LOONGSON2_PERFCNT_EXL (1UL << 0)
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#define LOONGSON2_PERFCNT_KERNEL (1UL << 1)
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#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2)
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#define LOONGSON2_PERFCNT_USER (1UL << 3)
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#define LOONGSON2_PERFCNT_INT_EN (1UL << 4)
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#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31)
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/* Loongson2 performance counter register */
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#define read_c0_perfctrl() __read_64bit_c0_register($24, 0)
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#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val)
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#define read_c0_perfcnt() __read_64bit_c0_register($25, 0)
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#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val)
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static struct loongson2_register_config {
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unsigned int ctrl;
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unsigned long long reset_counter1;
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unsigned long long reset_counter2;
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int cnt1_enabled, cnt2_enabled;
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} reg;
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static char *oprofid = "LoongsonPerf";
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static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id);
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/* Compute all of the registers in preparation for enabling profiling. */
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static void loongson2_reg_setup(struct op_counter_config *cfg)
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{
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unsigned int ctrl = 0;
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reg.reset_counter1 = 0;
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reg.reset_counter2 = 0;
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/* Compute the performance counter ctrl word. */
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/* For now count kernel and user mode */
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if (cfg[0].enabled) {
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ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event);
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reg.reset_counter1 = 0x80000000ULL - cfg[0].count;
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}
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if (cfg[1].enabled) {
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ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event);
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reg.reset_counter2 = (0x80000000ULL - cfg[1].count);
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}
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if (cfg[0].enabled || cfg[1].enabled) {
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ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN;
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if (cfg[0].kernel || cfg[1].kernel)
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ctrl |= LOONGSON2_PERFCNT_KERNEL;
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if (cfg[0].user || cfg[1].user)
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ctrl |= LOONGSON2_PERFCNT_USER;
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}
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reg.ctrl = ctrl;
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reg.cnt1_enabled = cfg[0].enabled;
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reg.cnt2_enabled = cfg[1].enabled;
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void loongson2_cpu_setup(void *args)
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{
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uint64_t perfcount;
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perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1;
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write_c0_perfcnt(perfcount);
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}
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static void loongson2_cpu_start(void *args)
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{
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/* Start all counters on current CPU */
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if (reg.cnt1_enabled || reg.cnt2_enabled)
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write_c0_perfctrl(reg.ctrl);
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}
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static void loongson2_cpu_stop(void *args)
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{
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/* Stop all counters on current CPU */
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write_c0_perfctrl(0);
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memset(®, 0, sizeof(reg));
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}
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static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id)
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{
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uint64_t counter, counter1, counter2;
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struct pt_regs *regs = get_irq_regs();
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int enabled;
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/*
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* LOONGSON2 defines two 32-bit performance counters.
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* To avoid a race updating the registers we need to stop the counters
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* while we're messing with
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* them ...
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*/
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/* Check whether the irq belongs to me */
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enabled = read_c0_perfctrl() & LOONGSON2_PERFCNT_INT_EN;
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if (!enabled)
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return IRQ_NONE;
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enabled = reg.cnt1_enabled | reg.cnt2_enabled;
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if (!enabled)
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return IRQ_NONE;
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counter = read_c0_perfcnt();
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counter1 = counter & 0xffffffff;
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counter2 = counter >> 32;
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if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) {
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if (reg.cnt1_enabled)
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oprofile_add_sample(regs, 0);
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counter1 = reg.reset_counter1;
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}
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if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) {
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if (reg.cnt2_enabled)
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oprofile_add_sample(regs, 1);
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counter2 = reg.reset_counter2;
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}
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write_c0_perfcnt((counter2 << 32) | counter1);
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return IRQ_HANDLED;
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}
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static int __init loongson2_init(void)
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{
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return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler,
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IRQF_SHARED, "Perfcounter", oprofid);
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}
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static void loongson2_exit(void)
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{
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write_c0_perfctrl(0);
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free_irq(LOONGSON2_PERFCNT_IRQ, oprofid);
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}
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struct op_mips_model op_model_loongson2_ops = {
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.reg_setup = loongson2_reg_setup,
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.cpu_setup = loongson2_cpu_setup,
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.init = loongson2_init,
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.exit = loongson2_exit,
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.cpu_start = loongson2_cpu_start,
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.cpu_stop = loongson2_cpu_stop,
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.cpu_type = LOONGSON2_CPU_TYPE,
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.num_counters = 2
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};
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