a2ca78cee1
Parts that have on-chip L2 SRAM cannot safely utilize writeback caching mode, so reject any attempts to use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
65 lines
2.2 KiB
C
65 lines
2.2 KiB
C
/*
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* Do some checking to make sure things are OK
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*
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* Copyright 2007-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <asm/fixed_code.h>
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#include <mach/anomaly.h>
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#include <asm/clocks.h>
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#ifdef CONFIG_BFIN_KERNEL_CLOCK
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# if (CONFIG_VCO_HZ > CONFIG_MAX_VCO_HZ)
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# error "VCO selected is more than maximum value. Please change the VCO multipler"
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# endif
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# if (CONFIG_SCLK_HZ > CONFIG_MAX_SCLK_HZ)
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# error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
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# endif
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# if (CONFIG_SCLK_HZ < CONFIG_MIN_SCLK_HZ)
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# error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
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# endif
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# if (ANOMALY_05000273) && (CONFIG_SCLK_HZ * 2 > CONFIG_CCLK_HZ)
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# error "ANOMALY 05000273, please make sure CCLK is at least 2x SCLK"
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# endif
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# if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ) && (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ) && (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
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# error "Please select sclk less than cclk"
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# endif
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#endif /* CONFIG_BFIN_KERNEL_CLOCK */
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#if CONFIG_BOOT_LOAD < FIXED_CODE_END
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# error "The kernel load address must be after the fixed code section"
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#endif
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#if (CONFIG_BOOT_LOAD & 0x3)
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# error "The kernel load address must be 4 byte aligned"
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#endif
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/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
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#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
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# error "The kernel load address is too high; keep it below 10meg for safety"
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#endif
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#if ANOMALY_05000448
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# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
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#endif
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/* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */
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#if ANOMALY_05000220 && \
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((defined(CONFIG_BFIN_EXTMEM_WRITEBACK) && !defined(CONFIG_BFIN_L2_DCACHEABLE)) || \
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(!defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) && defined(CONFIG_BFIN_L2_WRITEBACK)))
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# error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB.
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#endif
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#if ANOMALY_05000475 && \
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(defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK))
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# error "Anomaly 475 does not allow you to use Write Back cache with L2 or External Memory"
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#endif
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