7d12e780e0
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* EHCI HCD (Host Controller Driver) PCI Bus Glue.
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*
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* Copyright (c) 2000-2004 by David Brownell
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef CONFIG_PCI
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#error "This file is PCI bus glue. CONFIG_PCI must be defined."
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#endif
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/*-------------------------------------------------------------------------*/
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/* called after powerup, by probe or system-pm "wakeup" */
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static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
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{
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u32 temp;
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int retval;
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/* optional debug port, normally in the first BAR */
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temp = pci_find_capability(pdev, 0x0a);
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if (temp) {
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pci_read_config_dword(pdev, temp, &temp);
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temp >>= 16;
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if ((temp & (3 << 13)) == (1 << 13)) {
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temp &= 0x1fff;
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ehci->debug = ehci_to_hcd(ehci)->regs + temp;
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temp = readl(&ehci->debug->control);
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ehci_info(ehci, "debug port %d%s\n",
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HCS_DEBUG_PORT(ehci->hcs_params),
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(temp & DBGP_ENABLED)
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? " IN USE"
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: "");
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if (!(temp & DBGP_ENABLED))
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ehci->debug = NULL;
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}
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}
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/* we expect static quirk code to handle the "extended capabilities"
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* (currently just BIOS handoff) allowed starting with EHCI 0.96
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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retval = pci_set_mwi(pdev);
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if (!retval)
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ehci_dbg(ehci, "MWI active\n");
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ehci_port_power(ehci, 0);
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return 0;
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}
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/* called during probe() after chip reset completes */
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static int ehci_pci_setup(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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u32 temp;
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int retval;
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ehci->caps = hcd->regs;
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ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
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dbg_hcs_params(ehci, "reset");
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dbg_hcc_params(ehci, "reset");
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/* ehci_init() causes memory for DMA transfers to be
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* allocated. Thus, any vendor-specific workarounds based on
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* limiting the type of memory used for DMA transfers must
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* happen before ehci_init() is called. */
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_NVIDIA:
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/* NVidia reports that certain chips don't handle
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* QH, ITD, or SITD addresses above 2GB. (But TD,
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* data buffer, and periodic schedule are normal.)
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*/
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switch (pdev->device) {
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case 0x003c: /* MCP04 */
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case 0x005b: /* CK804 */
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case 0x00d8: /* CK8 */
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case 0x00e8: /* CK8S */
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if (pci_set_consistent_dma_mask(pdev,
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DMA_31BIT_MASK) < 0)
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ehci_warn(ehci, "can't enable NVidia "
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"workaround for >2GB RAM\n");
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break;
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}
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break;
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}
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/* cache this readonly data; minimize chip reads */
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ehci->hcs_params = readl(&ehci->caps->hcs_params);
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retval = ehci_halt(ehci);
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if (retval)
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return retval;
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/* data structure init */
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retval = ehci_init(hcd);
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if (retval)
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return retval;
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switch (pdev->vendor) {
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case PCI_VENDOR_ID_TDI:
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if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
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ehci->is_tdi_rh_tt = 1;
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tdi_reset(ehci);
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}
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break;
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case PCI_VENDOR_ID_AMD:
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/* AMD8111 EHCI doesn't work, according to AMD errata */
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if (pdev->device == 0x7463) {
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ehci_info(ehci, "ignoring AMD8111 (errata)\n");
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retval = -EIO;
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goto done;
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}
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break;
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case PCI_VENDOR_ID_NVIDIA:
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switch (pdev->device) {
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/* Some NForce2 chips have problems with selective suspend;
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* fixed in newer silicon.
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*/
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case 0x0068:
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pci_read_config_dword(pdev, PCI_REVISION_ID, &temp);
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if ((temp & 0xff) < 0xa4)
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ehci->no_selective_suspend = 1;
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break;
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}
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break;
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}
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if (ehci_is_TDI(ehci))
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ehci_reset(ehci);
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/* at least the Genesys GL880S needs fixup here */
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temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
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temp &= 0x0f;
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if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
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ehci_dbg(ehci, "bogus port configuration: "
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"cc=%d x pcc=%d < ports=%d\n",
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HCS_N_CC(ehci->hcs_params),
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HCS_N_PCC(ehci->hcs_params),
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HCS_N_PORTS(ehci->hcs_params));
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switch (pdev->vendor) {
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case 0x17a0: /* GENESYS */
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/* GL880S: should be PORTS=2 */
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temp |= (ehci->hcs_params & ~0xf);
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ehci->hcs_params = temp;
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break;
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case PCI_VENDOR_ID_NVIDIA:
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/* NF4: should be PCC=10 */
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break;
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}
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}
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/* Serial Bus Release Number is at PCI 0x60 offset */
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pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
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/* Workaround current PCI init glitch: wakeup bits aren't
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* being set from PCI PM capability.
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*/
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if (!device_can_wakeup(&pdev->dev)) {
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u16 port_wake;
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pci_read_config_word(pdev, 0x62, &port_wake);
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if (port_wake & 0x0001)
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device_init_wakeup(&pdev->dev, 1);
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}
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#ifdef CONFIG_USB_SUSPEND
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/* REVISIT: the controller works fine for wakeup iff the root hub
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* itself is "globally" suspended, but usbcore currently doesn't
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* understand such things.
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*
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* System suspend currently expects to be able to suspend the entire
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* device tree, device-at-a-time. If we failed selective suspend
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* reports, system suspend would fail; so the root hub code must claim
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* success. That's lying to usbcore, and it matters for for runtime
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* PM scenarios with selective suspend and remote wakeup...
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*/
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if (ehci->no_selective_suspend && device_can_wakeup(&pdev->dev))
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ehci_warn(ehci, "selective suspend/wakeup unavailable\n");
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#endif
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retval = ehci_pci_reinit(ehci, pdev);
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done:
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return retval;
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}
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_PM
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/* suspend/resume, section 4.3 */
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/* These routines rely on the PCI bus glue
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* to handle powerdown and wakeup, and currently also on
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* transceivers that don't need any software attention to set up
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* the right sort of wakeup.
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* Also they depend on separate root hub suspend/resume.
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*/
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static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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unsigned long flags;
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int rc = 0;
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if (time_before(jiffies, ehci->next_statechange))
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msleep(10);
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/* Root hub was already suspended. Disable irq emission and
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* mark HW unaccessible, bail out if RH has been resumed. Use
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* the spinlock to properly synchronize with possible pending
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* RH suspend or resume activity.
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*
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* This is still racy as hcd->state is manipulated outside of
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* any locks =P But that will be a different fix.
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*/
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spin_lock_irqsave (&ehci->lock, flags);
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if (hcd->state != HC_STATE_SUSPENDED) {
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rc = -EINVAL;
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goto bail;
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}
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writel (0, &ehci->regs->intr_enable);
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(void)readl(&ehci->regs->intr_enable);
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/* make sure snapshot being resumed re-enumerates everything */
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if (message.event == PM_EVENT_PRETHAW) {
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ehci_halt(ehci);
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ehci_reset(ehci);
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}
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clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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bail:
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spin_unlock_irqrestore (&ehci->lock, flags);
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// could save FLADJ in case of Vaux power loss
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// ... we'd only use it to handle clock skew
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return rc;
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}
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static int ehci_pci_resume(struct usb_hcd *hcd)
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{
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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unsigned port;
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval = -EINVAL;
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// maybe restore FLADJ
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if (time_before(jiffies, ehci->next_statechange))
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msleep(100);
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/* Mark hardware accessible again as we are out of D3 state by now */
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set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
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/* If CF is clear, we lost PCI Vaux power and need to restart. */
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if (readl(&ehci->regs->configured_flag) != FLAG_CF)
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goto restart;
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/* If any port is suspended (or owned by the companion),
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* we know we can/must resume the HC (and mustn't reset it).
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* We just defer that to the root hub code.
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*/
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for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
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u32 status;
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port--;
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status = readl(&ehci->regs->port_status [port]);
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if (!(status & PORT_POWER))
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continue;
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if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
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usb_hcd_resume_root_hub(hcd);
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return 0;
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}
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}
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restart:
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ehci_dbg(ehci, "lost power, restarting\n");
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usb_root_hub_lost_power(hcd->self.root_hub);
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/* Else reset, to cope with power loss or flush-to-storage
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* style "resume" having let BIOS kick in during reboot.
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*/
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(void) ehci_halt(ehci);
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(void) ehci_reset(ehci);
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(void) ehci_pci_reinit(ehci, pdev);
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/* emptying the schedule aborts any urbs */
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spin_lock_irq(&ehci->lock);
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if (ehci->reclaim)
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end_unlink_async (ehci);
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ehci_work(ehci);
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spin_unlock_irq(&ehci->lock);
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/* restart; khubd will disconnect devices */
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retval = ehci_run(hcd);
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/* here we "know" root ports should always stay powered */
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ehci_port_power(ehci, 1);
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return retval;
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}
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#endif
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static const struct hc_driver ehci_pci_hc_driver = {
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.description = hcd_name,
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.product_desc = "EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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/*
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* generic hardware linkage
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*/
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2,
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/*
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* basic lifecycle operations
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*/
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.reset = ehci_pci_setup,
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.start = ehci_run,
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#ifdef CONFIG_PM
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.suspend = ehci_pci_suspend,
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.resume = ehci_pci_resume,
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#endif
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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/*
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* managing i/o requests and associated device resources
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*/
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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/*
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* scheduling support
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*/
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.get_frame_number = ehci_get_frame,
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/*
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* root hub support
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*/
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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};
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/*-------------------------------------------------------------------------*/
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/* PCI driver selection metadata; PCI hotplugging uses this */
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static const struct pci_device_id pci_ids [] = { {
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/* handle any USB 2.0 EHCI controller */
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PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_EHCI, ~0),
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.driver_data = (unsigned long) &ehci_pci_hc_driver,
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},
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{ /* end: all zeroes */ }
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};
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MODULE_DEVICE_TABLE(pci, pci_ids);
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/* pci driver glue; this is a "new style" PCI driver module */
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static struct pci_driver ehci_pci_driver = {
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.name = (char *) hcd_name,
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.id_table = pci_ids,
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.probe = usb_hcd_pci_probe,
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.remove = usb_hcd_pci_remove,
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#ifdef CONFIG_PM
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.suspend = usb_hcd_pci_suspend,
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.resume = usb_hcd_pci_resume,
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#endif
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.shutdown = usb_hcd_pci_shutdown,
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};
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