253b0887b3
This moves out the old legacy CPG clocks to their own file, and converts over the existing users. With these clocks going away and each CPU dealing with them on their own, CPUs can gradually move over to the new interface. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
142 lines
3.2 KiB
C
142 lines
3.2 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
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*
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* SH7786 support for the clock framework
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*
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* Copyright (C) 2008, 2009 Renesas Solutions Corp.
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* Kuninori Morimoto <morimoto.kuninori@renesas.com>
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*
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* Based on SH7785
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* Copyright (C) 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int ifc_divisors[] = { 1, 2, 4, 1 };
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static int sfc_divisors[] = { 1, 1, 4, 1 };
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static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
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24, 32, 1, 1, 1, 1, 1, 1 };
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static int mfc_divisors[] = { 1, 1, 4, 1 };
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static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
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24, 32, 1, 48, 1, 1, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
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}
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static struct clk_ops sh7786_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (ctrl_inl(FRQMR1) & 0x000f);
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return clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7786_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
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return clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7786_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
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return clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7786_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7786_clk_ops[] = {
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&sh7786_master_clk_ops,
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&sh7786_module_clk_ops,
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&sh7786_bus_clk_ops,
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&sh7786_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7786_clk_ops))
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*ops = sh7786_clk_ops[idx];
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}
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static unsigned long shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
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return clk->parent->rate / sfc_divisors[idx];
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}
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static struct clk_ops sh7786_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7786_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7786_shyway_clk_ops,
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};
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static unsigned long ddr_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
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return clk->parent->rate / mfc_divisors[idx];
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}
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static struct clk_ops sh7786_ddr_clk_ops = {
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.recalc = ddr_clk_recalc,
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};
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static struct clk sh7786_ddr_clk = {
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.name = "ddr_clk",
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.flags = CLK_ENABLE_ON_INIT,
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.ops = &sh7786_ddr_clk_ops,
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};
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/*
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* Additional SH7786-specific on-chip clocks that aren't already part of the
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* clock framework
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*/
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static struct clk *sh7786_onchip_clocks[] = {
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&sh7786_shyway_clk,
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&sh7786_ddr_clk,
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};
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int __init arch_clk_init(void)
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{
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struct clk *clk;
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int i, ret = 0;
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cpg_clk_init();
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clk = clk_get(NULL, "master_clk");
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for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
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struct clk *clkp = sh7786_onchip_clocks[i];
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clkp->parent = clk;
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ret |= clk_register(clkp);
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}
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clk_put(clk);
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return ret;
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}
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